Fujitsu MHV2060AS, MHV2080AS, MHV2040AS manual Digital PLL circuit, FIR circuit, D converter circuit

Models: MHV2060AS MHV2080AS MHV2040AS

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4.6 Read/write Circuit

(3) FIR circuit

This circuit is 10-tap sampled analog transversal filter circuit that equalizes the head read signal to the Modified Extended Partial Response (MEEPR) waveform.

(4) A/D converter circuit

This circuit changes Sampled Read Data Pulse from the FIR circuit into Digital Read Data.

(5) Viterbi detection circuit

The sample hold waveform output from the flash digitizer circuit is sent to the Viterbi detection circuit. The Viterbi detection circuit demodulates data according to the survivor path sequence.

4.6.4 Digital PLL circuit

The drive uses constant density recording to increase total capacity. This is different from the conventional method of recording data with a fixed data transfer rate at all data area. In the constant density recording method, data area is divided into zones by radius and the data transfer rate is set so that the recording density of the inner cylinder of each zone is nearly constant. The drive divides data area into 30 zones to set the data transfer rate.

The MPU set the data transfer rate setup data (SD/SC) to the RDC that includes the Digital PLL circuit to change the data transfer rate.

C141-E221

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Page 67
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Fujitsu MHV2060AS, MHV2080AS, MHV2040AS Digital PLL circuit, FIR circuit, D converter circuit, Viterbi detection circuit