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Fujitsu MHV2060AS, MHV2080AS, MHV2040AS manual Logical Interface, Dmarq

Models: MHV2060AS MHV2080AS MHV2040AS

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Interface

[Signal]	[I/O]	[Description]
DMARQ	O	This signal is used for DMA transfer between the host system and
		the device. The device asserts this signal when the device
		completes the preparation of DMA data transfer to the host
		system (at reading) or from the host system (at writing).
		The direction of data transfer is controlled by the DIOR and
		DIOW signals. This signal hand shakes with the DMACK-signal.
		In other words, the device negates the DMARQ signal after the
		host system asserts the DMACK signal. When there is other data
		to be transferred, the device asserts the DMARQ signal again.
		When the DMA data transfer is performed, IOCS16-, CS0- and
		CS1- signals are not asserted. The DMA data transfer is a 16-bit
		data transfer.
+5 VDC	I	+5 VDC power supplying to the device.
GND	-	Grounded signal at each signal wire.
Note:

“I” indicates input signal from the host to the device.

“O” indicates output signal from the device to the host.

“I/O” indicates common output or bi-directional signal between the host and the device.

5.2 Logical Interface

The device can operate for command execution in either address-specified mode; cylinder-head-sector (CHS) or Logical block address (LBA) mode. The IDENTIFY DEVICE information indicates whether the device supports the LBA mode. When the host system specifies the LBA mode by setting bit 6 in the Device/Head register to 1, HS3 to HS0 bits of the Device/Head register indicates the head No. under the LBA mode, and all bits of the Cylinder High, Cylinder Low, and Sector Number registers are LBA bits.

The sector No. under the LBA mode proceeds in the ascending order with the start point of LBA0 (defined as follows).

LBA0 = [Cylinder 0, Head 0, Sector 1]

Even if the host system changes the assignment of the CHS mode by the INITIALIZE DEVICE PARAMETER command, the sector LBA address is not changed.

LBA = [((Cylinder No.) ⋅ (Number of head) + (Head No.)) ⋅ (Number of sector/track)] + (Sector No.) − 1

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C141-E221

Image 82

Fujitsu MHV2060AS, MHV2080AS, MHV2040AS manual Logical Interface, Dmarq

Contents

MHV2080AS, MHV2060AS, MHV2040AS Disk Drive Product ManualFor Safe Operation Handling of This ManualRevision History This page is intentionally left blank Preface Overview of ManualOperating Environment Conventions for Alert MessagesConventions Liability Exception This page is intentionally left blank Important Alert Messages Important Alert ItemsDamage Interface cable connection This page is intentionally left blank MHV2080AS Disk Drive Maintenance ManualManual Organization Disk Drive Product ManualThis page is intentionally left blank Contents Installation Conditions Theory of Device OperationContents Interface101 Write Multiple EXT X’39’ Option customizing Operations Glossary GL-1 Acronyms and Abbreviations AB-1 Index IN-1 Illustrations FiguresExecution example of Read Multiple command Tables Examples of model names and product numbers127 This page is intentionally left blank Device Overview Functions and performance FeaturesAdaptability Connection to ATA interface Error correction and retry by ECCHigh resistance against shock Data bufferSpecifications 1 Device SpecificationsSpecifications summary MHV2080AS MHV2060AS MHV2040ASModel and product number Examples of model names and product numbersInput Voltage Power RequirementsRipple Current Requirements and Power Dissipation Current and power dissipationPower on/off sequence Environmental SpecificationsCurrent fluctuation Typ. at +5 V when power is turned on Environmental specificationsAcoustic Noise Acoustic noise specificationShock and vibration specification Shock and VibrationReliability Service lifeData assurance in the event of power failure Mean time between failures MtbfPositioning error Error RateUnrecoverable read error Media DefectsAdvanced Power Management Advanced Power Management This page is intentionally left blank Device Configuration Device Configuration 2 1 drive connection System ConfigurationATA interface Read/write circuit2 drives configuration 3 2 drives connectionInstallation Conditions Dimensions DimensionsIntegration Guidance C141-E144 MountingOrientation Limitation of mounting FramePCA Location of breather Ambient temperature Service area Handling cautionsHandling cautions Device connector Cable ConnectionsDevice connection Cable connector specificationsCable connector specifications FCIPower supply connector CN1 Jumper SettingsLocation of setting jumpers Factory default setting Master drive-slave drive settingCsel setting 14 Csel settingPower up in standby setting 16 Example 2 of cable selectTheory of Device Operation Disk OutlineSubassemblies SpindleServo circuit Circuit ConfigurationAir filter Spindle motor driver circuitPower supply configuration PCA Power-on Sequence Power-on operation sequenceSelf-calibration contents Self-calibrationCommand processing during self-calibration Execution timing of self-calibrationWrite circuit Read/write CircuitRead/write preamplifier PreAMP Write precompensationAGC circuit Read circuitProgrammable filter circuit D converter circuit Digital PLL circuitFIR circuit Viterbi detection circuitServo Control Servo control circuitServo burst capture circuit Power amplifierMicroprocessor unit MPU A converter DACDriver circuit VCM current sense resistor CSRData area Data-surface servo formatInner guard band Outer guard bandPhysical sector servo configuration on disk surface Servo frame format Seek operation Actuator motor controlOperation to move the head to the reference cylinder Track following operationStable rotation mode Start modeAcceleration mode Spindle motor controlThis page is intentionally left blank Interface Interface signals Physical InterfaceDA1 PDIAG-, Cblid DA0 DA2 Signal assignment on the connectorSignal assignment on the interface connector Dasp GNDStop MstrDiow DiorDasp PdiagCblid IordyLogical Interface DmarqI/O registers 1 I/O registersDA2 DA1 DA0 Data register X’1F0’ Command block registersError register X’1F1’ UNC IdnfFeatures register X’1F1’ Sector Count register X’1F2’Cylinder Low register X’1F4’ Sector Number register X’1F3’Cylinder High register X’1F5’ Status register X’1F7’ Device/Head register X’1F6’DEV HS3 HS2 HS1 HS0 BSYInterface Control block registers Command register X’1F7’Alternate Status register X’3F6’ Device Control register X’3F6’ Host CommandsCommand code and parameters HOB SrstCommand Name Command code and parameters 1Parameter Used Command code and parameters 2 EXT Write Multiple FUA EXT Flush Cache EXTHost Commands Command descriptions Host Commands Recalibrate X’10’ to X’1F’ Read Sectors X’20’ or X’21’ MSBEnd head No. / LBA MSB Write Sectors X’30’ or X’31’ 1F7HST Status information 1F6HDH Write Verify X’3C’ MSBRead Verify Sectors X’40’ or X’41’ Seek X’70’ to X’7F’ Execute Device Diagnostic X’90’ Diagnostic codeDevice responds to this command with the result of power-on Initialize Device Parameters X’91’ Download Microcode X’92’ Operation of Download Microcode Standby Immediate X’94’ or X’E0’ Unload Feature Unload Immediate Command Host Commands Standby X’96’ or X’E2’ Idle X’97’ or X’E3’ Interface Check Power Mode X’98’ or X’E5’ ’FF’Sleep X’99’ or X’E6’ Smart X’B0 Features register values subcommands and functions 1 Smart Disable Operations Features register values subcommands and functions 2Smart Enable Operations Smart Read LOG’DB’ Smart ENABLE/DISABLE Auto OFF-LINE Features register values subcommands and functions 3Smart Return Status Host Commands 1FF Format of device attribute value dataFormat of insurance failure threshold value data Data format version number Attribute IDAttribute value for the worst case so far Status FlagCurrent attribute value Raw attribute valueSelf-test execution status 10 Off-line data collection status11 Self-test execution status Failure prediction capability flag Off-line data collection capability12 Off-line data collection capability 13 Failure prediction capability flagCheck sum Error logging capability14 Error logging capability Insurance failure thresholdSmart error logging 16 Data format of Smart Summary Error Log Total number of drive errors Command data structureError data structure 17 Data format of Smart Comprehensive Error Log1FC Smart self-test18 Smart self-test log data format Self-test numberCurrent LBA under test 19 Selective self-test log data structureTest span Current span under test20 Selective self-test feature flags Feature FlagsSelective Self-test pending time min Device Configuration Freeze Device Configuration XB1Device Configuration Restore Device Configuration IdentifyDevice Configuration Identify FR = C2h Device Configuration Restore FR = C0hDevice Configuration Freeze Lock FR = C1h Device Configuration SET FR = C3hInterface 21 Device Configuration Identify data structure 1/2 21 Device Configuration Identify data structure 2/2 Execution example of Read Multiple command Read Multiple X’C4’MSB Write Multiple X’C5’ Interface SET Multiple Mode X’C6’ Interface Read DMA X’C8’ or X’C9’ MSBEnd head No. / LBA MSB Write DMA X’CA’ or X’CB’ Interface Read Buffer X’E4’ Flush Cache X’E7’ Write Buffer X’E8’ Identify Device X’EC’ Identify Device DMA X’EE’ 22 Information to be read by Identify Device command 1 ’3FFF’22 Information to be read by Identify Device command 2 3FFF Command without interrupt supports 2, 4, 8 and 16 sectors = Supports the Host Protected Area feature set = Supports the CFA Compact Flash Association feature set Interface Write Stream EXT Interface Host Commands Word Bit Reserved Security level High, 1 Maximum ’BB’ SET Features X’EF’23 Features register values and settable modes ’CC’Data Transfer Mode Advanced Power Management APM Automatic Acoustic Management AAM 24 Contents of Security SET Password data Interface When the user password is selected When the master password is selectedSecurity UNLOCKX’F2’ Interface Security Erase Prepare X’F3’ Security Erase Unit X’F4’ Security Freeze Lock X’F5’ Interface 26 Contents of security password Interface Read Native MAX Address X’F8’ SET MAX X’F9’ SET MAX AddressSET MAX SET Password FR = 01h SET MAX Lock FR = 02h SET MAX Unlock FR = 03h SET MAX Freeze Lock FR = 04h Host Commands Read Sectors EXT X’24’ Option customizing Description Read DMA EXT X’25’ Option customizing Description Error reporting conditions Read Multiple EXT X’29’ Option customizing Description Read LOG EXT X2F Optional command Customize Description Host Commands Write Sectors EXT X’34’ Option customizing Description Write DMA EXT X’35’ Option customizing Description Error reporting conditions SET MAX Address EXT X’37’ Option customizing DescriptionSET MAX LBA Write Multiple EXT X’39’ Option customizing Description Write DMA FUA EXT X’3D’ Option customizing Description Write LOG EXT X’3F’ Optional command Customize Description Host Commands Read Verify Sectors EXT X’42 Option customizing Description Write Multiple FUA EXT X’CE’ Option customizing Description Error reporting conditions Flush Cache EXT X’EA’ Option customizing DescriptionError posting 27 Command code and parameters 127 Command code and parameters 2 PIO Data transferring commands from device to host Command ProtocolExecute Device Diagnostic Initialize Device Parameters Read Sectors Command protocol Protocol for command abort PIO Data transferring commands from host to device Write Sectors command protocol Commands without data transfer Read Multiple EXT Write Multiple EXT/FUA EXT Sleep Other commandsDMA data transfer commands Read DMA EXT Write DMA EXT/FUA EXT Indentify Device DMANormal DMA data transfer Ultra DMA Feature Set OverviewUltra DMA data in commands Phases of operationInitiating an Ultra DMA data in burst Pausing an Ultra DMA data in burst Data in transferTerminating an Ultra DMA data in burst DmarqUltra DMA Feature Set Interface Ultra DMA data out commands Initiating an Ultra DMA data out burstPausing an Ultra DMA data out burst Data out transferTerminating an Ultra DMA data out burst Interface Ultra DMA CRC rules DIOR-HDMARDY-HSTROBE Series termination required for Ultra DMA28 Recommended series termination for Ultra DMA DIOW-STOPPIO data transfer TimingPIO data transfer timing 10 Multiword DMA data transfer timing mode Multiword data transferUltra DMA data transfer 11 Initiating an Ultra DMA data in burstName Mode Comment Strobe29 Ultra DMA data burst timing requirements 2 MIN MAXMode Name Comment 30 Ultra DMA sender and recipient timing requirementsDD150 at device Dstrobe at host Sustained Ultra DMA data in burstDstrobe at device DD150 at hostDmack Host pausing an Ultra DMA data in burstDmarq HdmardyDevice terminating an Ultra DMA data in burst StopHost Host terminating an Ultra DMA data in burstDA0, DA1, DA2 CS0, CS1 16 Initiating an Ultra DMA data out burst Hstrobe at host DD150 at host Sustained Ultra DMA data out burstHstrobe at device DD150 at device Device DMACK- host Stop host DDMARDY- device Device pausing an Ultra DMA data out burstHstrobe host DD150 Host Host terminating an Ultra DMA data out burst 19 Host terminating an Ultra DMA data out burstDmarq device DMACK- host Device terminating an Ultra DMA data out burstDD150 Host Master and slave devices are present 2-drives configuration Power-on and resetOnly master device is present Operations Device Response to the Reset Response to power-onResponse to hardware reset Response to power-onResponse to hardware reset Response to software reset Response to software resetResponse to diagnostic command Response to diagnostic commandActive mode Power SavePower save mode Active idle modeStandby mode Sleep modeDefect Processing Power commandsSpare area Sector slip processing Alternating processing for defective sectorsTrack slip processing Automatic alternating processing Automatic alternating processingData buffer structure Read-ahead Cache8MB buffer 8,388,608 bytes Data that is a target of caching Commands that are targets of cachingCaching operation Invalidating caching-target dataSmart Using the read segment buffer Miss-hitSequential hit Full hit Partial hit Cache operation Command that are targets of cachingWrite Cache Invalidation of cached dataCaching function when power supply is turned on Status report in the event of an errorReset response Enabling and disablingWrite Cache This page is intentionally left blank Glossary PIO Programmed input-output Power save modeRotational delay PositioningStatus VCMThis page is intentionally left blank Acronyms and Abbreviations This page is intentionally left blank Index AAMIndex Host pausing ultra DMA data Read Sectors Command Read Native MAX AddressSurface temperature measurement This page is intentionally left blank Comment Form JapanThis page is intentionally left blank C141-E221-02EN This page is intentionally left blank