(2)Programmable filter
The programmable filter circuit has a
(3)FIR (Digital Finite Impulse Response Equalization Filter) adaptation circuit
The FIR provides support for changing equalization needs from head to head and zone to zone. The FIR is a specialized digital filter with ten independently controlled coefficients.
(4)Viterbi detection circuit
The Viterbi detection circuit demodulates data according to the survivor path sequence.
(5)Data separator circuit
The data separator circuit generates clocks in synchronization with the output of the adaptive equalizer circuit. To write data, the VFO circuit generates clocks in synchronization with the clock signals from a synthesizer.
(6)48/51 GCR decoder
This circuit converts the
4.6.4Time base generator circuit
The drive uses constant density recording to increase total capacity. This is different from the conventional method of recording data with a fixed data transfer rate at all data area. In the constant density recording method, data area is divided into zones by radius and the data transfer rate is set so that the recording density of the inner cylinder of each zone is nearly constant. The drive divides data area into 15 zones to set the data transfer rate. Table 4.2 describes the data transfer rate and recording density (BPI) of each zone.
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