2 System Board

Memory Controller Hub (82850)

The following table shows the features that are available in the MCH HostBridge/Controller.

 

Feature

Feature

 

 

 

•

Processor/System Bus:

• Accelerated Graphics Port (AGP) Interface:

 

❒ Supports on Pentium 4 processor at: 100 MHz System Bus

❒ Single 1.5V AGP PRO connector.

 

frequency (400 MHz Data Bus).

❒ AGP Rev 2.0 compliant, including AGP 4x data transfers and

 

❒ Provides an 8-deep In-Order Queue supporting up to eight

2x/4x Fast Write protocol.

 

outstanding transaction requests on the System bus.

❒ AGP 1.5V connector support with 1.5 V signalling only.

 

❒ Desktop optimized AGTL+ bus driver technology with inte-

❒ AGP PIPE# or SBA initiated accesses to DRAM is not

 

grated AGTL + termination resistors.

snooped

 

❒ Support for 32-bit System bus address.

❒ AGP FRAME initiated accesses to DRAM are snooped

 

 

(snooper identifies that data is coherent in cache memory).

 

 

❒ Hierarchical PCI configuration mechanism.

 

 

❒ Delayed transaction support for AGP-to-DRAM reads that

 

 

cannot be serviced immediately.

 

 

 

•

Memory Controller.

 

Direct Rambus:

 

 

❒ Dual Direct Rambus Channels operating in lock-step (both

 

 

channels must be populated with a memory module).

 

 

Supporting 300 MHz or 400 MHz.

 

 

❒ RDRAM 128 Mb, 256 Mb devices.

 

 

❒ Minimum upgrade increment of 32 MB using 128 Mbit

 

 

DRAM technology.

 

 

❒ Up to 64 Direct Rambus devices.

 

 

Dual channel maximum memory array size is:

 

 

— 1 GB using 128 Mbit DRAM technology.

 

 

— 2 GB using 256 Mbit DRAM technology.

 

 

❒ Up to 8 simultaneous open pages:

 

 

— 1 KByte page size support for 128 Mbit and 256 Mbit

 

 

RDRAM devices.

 

 

— 2 KByte page size support for 256 Mbit RDRAM devices.

 

•Hub Link 8-bit Interface to ICH2:

❒High-speed interconnect between the MCH and ICH2 (266 MB/sec).

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