![2.1.1 Simultaneous multi-threading](/images/new-backgrounds/108464/10846465x1.webp)
2.1.1 Simultaneous multi-threading
As a permanent requirement for performance improvements at the application level, simultaneous
SMT is activated by default when an OS that supports it is loaded. On a
Simultaneous
The SMT mode maximizes the usage of the execution units. In the POWER5 chip, more rename registers have been introduced (for Floating Point operation, rename registers are increased to 120), that are essential for
Enhanced SMT features
To improve SMT performance for various workload mixes and provide robust quality of service, POWER5 provides two features:
Dynamic resource balancing
–The objective of dynamic resource balancing is to ensure that the two threads executing on the same processor flow smoothly through the system.
–Depending on the situation, the POWER5 processor resource balancing logic has a different thread throttling mechanism.
Adjustable thread priority
–Adjustable thread priority lets software determine when one thread should have a greater (or lesser) share of execution resources.
–The POWER5 supports eight
ST operation
Not all applications benefit from SMT. Having threads executing on the same processor does not increase the performance of applications with execution unit limited performance or applications that consume all of the chip’s memory bandwidth. For this reason, the POWER5 processor supports the ST execution mode. In this mode, the POWER5 processor gives all of the physical resources to the active thread, enabling it to achieve higher performance than a POWER4
2.1.2 Dynamic power management
In current CMOS1 technologies, chip power is one of the most important design parameters. With the introduction of SMT, more instructions execute per cycle per processor core, thus increasing the core’s and the chip’s total switching power. To reduce switching power,
1complementary metal oxide semiconductor
Chapter 2. Architecture and technical overview 21