IBM P5 570 manual The POWER chip evolution, POWER5TM

POWER5 chips extensively use a fine-grained, dynamic clock-gating mechanism. This mechanism gates off clocks to a local clock buffer if dynamic power management logic knows that the set of latches that are driven by the buffer will not be used in the next cycle. This allows substantial power saving with no performance impact. In every cycle, the dynamic power management logic determines whether a local clock buffer that drives a set of latches can be clock-gated in the next cycle.

In addition to the switching power, leakage power has become a performance limiter. To reduce leakage power, the POWER5 chip uses transistors with low threshold voltage only in critical paths. The POWER5 chip also has a low-power mode, enabled when the system software instructs the hardware to execute both threads at the lowest available priority. In low power mode, instructions dispatch once every 32 cycles at most, further reducing switching power. The POWER5 chip uses this mode only when there is no ready task to run on either thread.

2.1.3 The POWER chip evolution

The p5-570 system complies with the RS/6000 platform architecture, which is an evolution of the PowerPC Common Hardware Reference Platform (CHRP) specifications. Figure 2-3shows the POWER chip evolution.

						POWER4+
						1.2 to 1.9 GHz
		Models 270, B80, and			POWER4	p615, p630,
		POWER3 SP Nodes			1.0 to 1.3
			Power3-II			p650, p655, p670
				RS64-IV	GHz	and p690
		333 / 375 /			p630, p650, p655,
64bit	SP Nodes		450	600 / 750	p670, and p690	Note: Not all
			RS64-III
	Power3			pSeries p620, p660,		processor speeds
			450
		200+		and p680		available on all
						models
			F80, H80, M80, S80
			RS64-II
		RS64-II	340
	RS64	262.5	H70		SOI
32bit	125	S7A
	S70

604e	+ SOI =
332 /
375	Copper =
F50

POWER4™

0.18 microns

1.0 to	1.0 to
1.3 GHz	1.3 GHz
Core	Core

Shared L2

Distributed Switch

2001

–Distributed Switch

–Shared L2

–LPAR

–Autonomic computing

–Chip multiprocessing

POWER4+

0.13 microns

1.2 to 1.2 to

1.9GHz 1.9 GHz

Core Core

Shared L2

Distributed Switch

2002-3

–Larger L2

–More LPARs

–High-speed Switch

POWER5TM

0.13 microns

1.5 to	1.5 to
1.9 GHz	1.9 GHz
Core	Core

	Shared L2
		Mem Ctl
Distributed Switch

2004

–Larger L2 and L3 caches

–Micro-partitioning

–Enhanced Distributed Switch

–Enhanced core parallelism

–Improved floating-point

–performance

–Faster memory environment

Figure 2-3 The POWER chip evolution

22p5-570 Technical Overview and Introduction