1
Chapter 1. General description
The IBM ^p5 570 rack-mount server is designed for greater application flexibility, with innovative technology, to capitalize on the e-business revolution at the midrange level for server environments. Introduced with the POWER4™ and POWER4+™ technology in 2001 and available from the 1-way entry-level through the 32-way high-end pSeries systems, the IBM POWER™ architecture achieved a new stage of capability characteristics by including features such as logical partitioning (LPAR). With POWER5™ microprocessor technology, the p5-570 is the first cost-effective, high-performance midrange UNIX server to include the next development of the IBM partitioning concept, Micro-Partitioning™.
Dynamic logical partitioning is supported from the 2-way p5-570 to the 16-way p5-570 system, allowing up to 16 dedicated partitions. In addition, the optional Advanced POWER Virtualization hardware feature enables a technology called Micro-Partitioning technology. The p5-570 system has been designed to support up to 160 partitions on a 16-way system. The Micro-Partitioning technology is an advanced feature of the POWER5 processor that enables multiple partitions to share a physical processor. The extended POWER Hypervisor controls dispatching the physical processors to each of the partitions using Micro-Partitioning technology. In addition to Micro-Partitioning technology, the Advanced POWER Virtualization feature enables sharing of network and storage adapters to satisfy the I/O requests of partitions that do not have a dedicated physical I/O adapter.
In combination with the extraordinary POWER5 processor, the Micro-Partitioning technology is designed to increase system management efficiency and lowers operating expenses through the multiple use of single physical resources that are installed in the p5-570 system.
Simultaneous multi-threading (SMT), a standard feature of POWER5 technology, enables two threads to be executed at the same time on a single processor. SMT is user-selectable with dedicated or processors from a shared pool for use by partitions using Micro-Partitioning technology.
The symmetric multiprocessor (SMP) p5-570 system features base 2-way, 4-way, 8-way,
12-way, and 16-way, 64-bit, copper-based, SOI-based POWER5 microprocessors running at
1.5GHz, 1.65 GHz, and 1.9 GHz with 36 MB off-chip Level 3 cache configurations. The system is based on a concept of system building blocks. The p5-570 building blocks are facilitated with the use of Processor interconnect and system SP Flex cables that enable as many as four 4-way p5-570 building blocks to be connected to achieve a true 16-way SMP
