IBM P5 570 manual 3.2Reliability, availability, and serviceability, 3.1.4Trial Capacity on Demand

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3.1.4Trial Capacity on Demand

Customers with CUoD featured systems must purchase the activation codes from IBM before the non-activated CUoD resources can be activated to meet the increased workload. However with the Trial Capacity on Demand feature, customers can activate the required non-activated CUoD resources immediately and, after that, proceed to purchase those resources from IBM or not. The HMC calls this feature Activate Immediate. A one-time no-cost activation for a maximum period of 30 consecutive days is available as a complementary service when access to CUoD resources is required immediately.

The following basic rules apply for the p5-570 system:

￿After the CUoD resources are activated, the customer must either buy all or part of the activated CUoD resources from IBM or return the activated CUoD resources to the system within 30 days.

￿Trial CUoD can only be used once.

There are several advantages to using this feature:

￿You can improve the response time to meet unpredictable increase in workload.

￿Customer can monitor the performance of the system after activating the CUoD resources before placing the order for activation codes.

￿It is useful when a CUoD permanent activation purchase is pending.

3.2Reliability, availability, and serviceability

Excellent quality and reliability are inherent in all aspects of the IBM Sserver p5 design and manufacturing. The fundamental objective of the design approach is to minimize outages. The RAS features help to ensure that the system operates when required, performs reliably, and efficiently handles any failures that may occur. This is achieved by using capabilities that are provided by both the hardware and AIX 5L.

The p5-570 as a POWER5 server improves on the RAS capabilities that are implemented in POWER4-based systems. Available RAS enhancements on POWER5 servers are:

￿Most firmware updates enable the system to remain operational.

￿ECC has been extended to inter-chip connections for the Fabric and Processor bus.

￿Partial L2 cache deallocation is possible.

￿Number of L3 cache line deletes improved from 2 to 10 for better self-healing capability.

The following sections describe the concepts that form the basis of leadership RAS features of IBM Sserver p5 systems in more detail.

3.2.1 Fault avoidance

p5 systems are built to keep errors from ever happening. This quality-based design includes such features as:

￿Reduced power consumption and cooler operating temperatures for increased reliability, enabled by the use of copper chip circuitry, SOI, and dynamic clock-gating

￿Mainframe-inspired components and technologies

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