2.11 USB2.0 Port 2 Connector CN2, Signal | Intel GENE-8310 instruction

Image 26

Intel GENE-8310 2.11 USB2.0 Port 2 Connector CN2, Primary IDE Hard Drive Connector CN3, SubCompact BoardG E N E - 8 3 1

Contents

6 Channel Audio & Mini PCI GENE-8310Intel Celeron M Processor Subcompact Board With LVDS, Ethernet SubCompact Board Copyright Notice Acknowledgments Packing List Chapter 1 General Information ContentsChapter 2 Quick Installation Guide Appendix A Programming The Watchdog Timer Chapter 3 Award BIOS SetupChapter 4 Driver Installation IRQ Mapping Chart Appendix BI/O Information I/O Address Map Chapter 1 General Information 1 General InformationChapter Multiple Display Modes Superb Performance and Controllable Power Usage1.1 Introduction Chapter 1 General Information Wide Expansion Capability AC-97 3D Surround 5.1 Channel Audio 1.2 Features48-bit Dual Channels LVDS TFT LCD 10/100Mbps Fast Ethernet Supports Type II CompactFlash Memory 1.3 Specifications System Display support Wake-up function Two 5 x 2 Pin Headers Support4 USB 2.0 Ports Does not Part No. 2007831011 Printed in Taiwan JAN Quick Installation GuideChapter 2 Quick Installation Guide 2.1 Safety Precautions 2.2 Location of Connectors and Jumpers Component Side The Height of Cooling System Depends on Customer Cooling Device Solder Side CFD1 DIMM1 The Height of Cooling System Depends on Customer Cooling Device 2.3 Mechanical DrawingComponent Side 103.51 0.58 3.23 8.89 0.00 72.39 0.58 114.30133.93 0.00 Label Jumpers2.4 List of Jumpers Function Connectors 2.5 List of Connectors CN17 Closed 2.6 Setting JumpersOpen 2.8 LCD Voltage Selection JP2 2.10 USB2.0 Port 1 Connector CN12.7 Clear CMOS Selection JP1 2.9 COM2 RI/+5V Selection JP5 2.11 USB2.0 Port 2 Connector CN2 2.12 Primary IDE Hard Drive Connector CN3 Name 2.13 Digital IO Connector CN4DIO Address is 801H 2.15 Serial Port COM2 Connector CN6 2.14 Front Panel CN5 2.16 Parallel Port Connector CN7 PinSignal 2.17 Dual Channel LVDS Connector CN82.18 4P Power Connector CN9 2.21 Audio Input/Output Connector CN12 2.19 TV-Out Connector CN102.20 DVI Connector CN11 2.24 IrDA Connector CN15 2.22 Ethernet 10/100Base-TX RJ-45 Phone Jack Connector CN132.23 External 5VSB/PWRGD Connector CN14 G E N E - 8 2.27 Serial Port COM1 Connector CN18 2.25 Fan Connector CN162.26 Mini-DIN PS/2 Connector CN17 2.30 Mini PCI Slot MPCI1 2.28 CRT Display Connector CN192.29 External Battery VBAT2 2.31 CompactFlash Disk Slot CFD1 SubCompact Board Award BIOS Setup Chapter 3 Award BIOS Setup System configuration verification 3.1 System Test and Initialization Advanced BIOS Features Entering SetupStandard CMOS Features Advanced Chipset Features Load Fail-Safe Defaults Power Management SetupPnP/PCI Configurations Load Optimized Defaults Exit Without Saving Set Supervisor/User PasswordSave and Exit Setup Driver Installation Chapter 4 Driver Installation Follow the sequence below to install the drivers 4.1 Installation Chapter4 Drivers Installation Step 4 - Install Realtek AC97 codec Driver Appendix A Programming the Watchdog Timer A-1 Programming the Watchdog TimerAppendix Appendix A Programming the Watchdog Timer A-2 Configuring Sequence DescriptionA.1 Programming 3 Exit the MB PnP Mode 1 Enter the MB PnP Mode2 Modify the Data of the Registers Appendix A Programming the Watchdog Timer A-4 Configure Control Index=02hWatchDog Timer Configuration Registers WatchDog Timer Time-out Value Register Index=73h, Default=00h WatchDog Timer Control Register Index=71h, Default=00hWatchDog Timer Configuration Register Index=72h, Default=00h Appendix A Programming the Watchdog Timer A-5 A.2 ITE8712 Watchdog Timer Initial Program game port enable mov cl call SetLogicDevice InitialOK CALL ReadConfigurationData CMP AL,12h JNE NotInitial NeedInitial STC RET ExitConfigurationMode ENDP CheckChip PROC NEAR MOV AL,20hCALL ReadConfigurationData CMP AL,87h JNE NotInitial MOV AL,21h RET NotInitial CLC RET CheckChip ENDP ReadConfigurationData PROC NEAR MOV DX,WORD PTR CSCfgPort+06h IN AL,DX RET ReadConfigurationData ENDP SetLogicDevice proc near push ax push cx xchg al,cl mov cl,07h END MainAppendix A Programming the Watchdog Timer A-10 call SuperioSetReg pop cx pop ax ret SetLogicDevice endp I/O Information Appendix B I/O Information B-1 Appendix B I/O Information B-2 B.1 I/O Address MapB.2 1st MB Memory Address Map Appendix B I/O Informaion B-3 B.3 IRQ Mapping ChartB.4 DMA Channel Assignments