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Intel GENE-8310 manual I/O Information, Appendix, SubCompact Board, G E N E - 8 3 1

Models: GENE-8310

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SubCompact Board	G E N E - 8 3 1 0

Appendix

I/O Information

Appendix B I/O Information B-1

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Intel GENE-8310 manual SubCompact Board, G E N E - 8 3 1, Appendix B I/O Information B-1

Contents

SubCompact Board GENE-8310Intel Celeron M Processor Subcompact Board With LVDS, Ethernet 6 Channel Audio & Mini PCICopyright Notice Acknowledgments Packing List Chapter 2 Quick Installation Guide ContentsChapter 1 General Information Chapter 4 Driver Installation Chapter 3 Award BIOS SetupAppendix A Programming The Watchdog Timer SubCompact BoardG E N E - 8 3 1 Appendix BI/O Information IRQ Mapping ChartG E N E - 8 3 1 General InformationChapter SubCompact BoardChapter 1 General Information Superb Performance and Controllable Power Usage1.1 Introduction Multiple Display ModesWide Expansion Capability Supports Type II CompactFlash Memory 1.2 Features48-bit Dual Channels LVDS TFT LCD 10/100Mbps Fast Ethernet AC-97 3D Surround 5.1 Channel AudioSystem 1.3 SpecificationsDisplay SubCompact Board Two 5 x 2 Pin Headers Support4 USB 2.0 Ports Does not support Wake-up functionSubCompact Board Quick Installation GuideChapter 2 Quick Installation Guide Chapter2.1 Safety Precautions G E N E - 8 3 1 2.2 Location of Connectors and Jumpers Component SideChapter 2 Quick Installation Guide SubCompact BoardG E N E - 8 3 1 Solder SideChapter 2 Quick Installation Guide SubCompact BoardSubCompact Board 2.3 Mechanical DrawingComponent Side Chapter 2 Quick Installation GuideG E N E - 8 3 1 Chapter 2 Quick Installation GuideSolder Side SubCompact BoardSubCompact Board Jumpers2.4 List of Jumpers Chapter 2 Quick Installation Guide2.5 List of Connectors ConnectorsCN17 Closed 2.6 Setting JumpersOpen Closed2.9 COM2 RI/+5V Selection JP5 2.10 USB2.0 Port 1 Connector CN12.7 Clear CMOS Selection JP1 2.8 LCD Voltage Selection JP2Signal 2.11 USB2.0 Port 2 Connector CN22.12 Primary IDE Hard Drive Connector CN3 SignalG E N E - 8 3 1 2.13 Digital IO Connector CN4DIO Address is 801H SubCompact BoardSignal 2.15 Serial Port COM2 Connector CN62.14 Front Panel CN5 SignalSignal 2.16 Parallel Port Connector CN7Signal SignalSignal 2.17 Dual Channel LVDS Connector CN82.18 4P Power Connector CN9 SignalSignal 2.19 TV-Out Connector CN102.20 DVI Connector CN11 2.21 Audio Input/Output Connector CN12Signal 2.22 Ethernet 10/100Base-TX RJ-45 Phone Jack Connector CN132.23 External 5VSB/PWRGD Connector CN14 2.24 IrDA Connector CN15PinSignal 2.25 Fan Connector CN162.26 Mini-DIN PS/2 Connector CN17 2.27 Serial Port COM1 Connector CN182.31 CompactFlash Disk Slot CFD1 2.28 CRT Display Connector CN192.29 External Battery VBAT2 2.30 Mini PCI Slot MPCI1G E N E - 8 3 1 SubCompact BoardSubCompact Board Award BIOS SetupChapter 3 Award BIOS Setup Chapter3.1 System Test and Initialization System configuration verificationAdvanced Chipset Features Entering SetupStandard CMOS Features Advanced BIOS FeaturesLoad Optimized Defaults Power Management SetupPnP/PCI Configurations Load Fail-Safe DefaultsSave and Exit Setup Set Supervisor/User PasswordExit Without Saving SubCompact Board Driver InstallationChapter 4 Driver Installation ChapterFollow the sequence below to install the drivers Chapter4 Drivers Installation 4.1 InstallationStep 4 - Install Realtek AC97 codec Driver SubCompact Board Programming the Watchdog TimerAppendix Appendix A Programming the Watchdog Timer A-1A.1 Programming Configuring Sequence DescriptionAppendix A Programming the Watchdog Timer A-2 3 Exit the MB PnP Mode 1 Enter the MB PnP Mode2 Modify the Data of the Registers SubCompact Board Configure Control Index=02hWatchDog Timer Configuration Registers Appendix A Programming the Watchdog Timer A-4Appendix A Programming the Watchdog Timer A-5 WatchDog Timer Control Register Index=71h, Default=00hWatchDog Timer Configuration Register Index=72h, Default=00h WatchDog Timer Time-out Value Register Index=73h, Default=00hA.2 ITE8712 Watchdog Timer Initial Program game port enable mov cl call SetLogicDevice InitialOK RET NotInitial CLC RET CheckChip ENDP ReadConfigurationData PROC NEAR RET ExitConfigurationMode ENDP CheckChip PROC NEAR MOV AL,20hCALL ReadConfigurationData CMP AL,87h JNE NotInitial MOV AL,21h CALL ReadConfigurationData CMP AL,12h JNE NotInitial NeedInitial STCMOV DX,WORD PTR CSCfgPort+06h IN AL,DX RET ReadConfigurationData ENDP call SuperioSetReg pop cx pop ax ret SetLogicDevice endp END MainAppendix A Programming the Watchdog Timer A-10 SetLogicDevice proc near push ax push cx xchg al,cl mov cl,07hG E N E - 8 3 1 I/O InformationAppendix SubCompact BoardAppendix B I/O Information B-2 B.1 I/O Address MapB.2 1st MB Memory Address Map SubCompact BoardG E N E - 8 3 1Appendix B I/O Informaion B-3 B.3 IRQ Mapping ChartB.4 DMA Channel Assignments SubCompact BoardG E N E - 8 3 1