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Intel GENE-8310 manual General Information, Chapter, SubCompact Board, G E N E - 8 3 1

Models: GENE-8310

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SubCompact Board	G E N E - 8 3 1 0

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Intel GENE-8310 manual Chapter, SubCompact Board, G E N E - 8 3 1, General Information 1

Contents

GENE-8310 Intel Celeron M Processor Subcompact Board With LVDS, Ethernet6 Channel Audio & Mini PCI SubCompact BoardCopyright Notice Acknowledgments Packing List Chapter 1 General Information ContentsChapter 2 Quick Installation Guide Appendix A Programming The Watchdog Timer Chapter 3 Award BIOS SetupChapter 4 Driver Installation Appendix B I/O InformationIRQ Mapping Chart SubCompact BoardG E N E - 8 3 1General Information ChapterSubCompact Board G E N E - 8 3 1Superb Performance and Controllable Power Usage 1.1 IntroductionMultiple Display Modes Chapter 1 General InformationWide Expansion Capability 1.2 Features 48-bit Dual Channels LVDS TFT LCD 10/100Mbps Fast EthernetAC-97 3D Surround 5.1 Channel Audio Supports Type II CompactFlash Memory1.3 Specifications SystemDisplay Two 5 x 2 Pin Headers Support 4 USB 2.0 Ports Does notsupport Wake-up function SubCompact BoardQuick Installation Guide Chapter 2 Quick Installation GuideChapter SubCompact Board2.1 Safety Precautions 2.2 Location of Connectors and Jumpers Component Side Chapter 2 Quick Installation GuideSubCompact Board G E N E - 8 3 1Solder Side Chapter 2 Quick Installation GuideSubCompact Board G E N E - 8 3 12.3 Mechanical Drawing Component SideChapter 2 Quick Installation Guide SubCompact BoardChapter 2 Quick Installation Guide Solder SideSubCompact Board G E N E - 8 3 1Jumpers 2.4 List of JumpersChapter 2 Quick Installation Guide SubCompact BoardConnectors 2.5 List of ConnectorsCN17 2.6 Setting Jumpers OpenClosed Closed2.10 USB2.0 Port 1 Connector CN1 2.7 Clear CMOS Selection JP12.8 LCD Voltage Selection JP2 2.9 COM2 RI/+5V Selection JP52.11 USB2.0 Port 2 Connector CN2 2.12 Primary IDE Hard Drive Connector CN3Signal Signal2.13 Digital IO Connector CN4 DIO Address is 801HSubCompact Board G E N E - 8 3 12.15 Serial Port COM2 Connector CN6 2.14 Front Panel CN5Signal Signal2.16 Parallel Port Connector CN7 SignalSignal Signal2.17 Dual Channel LVDS Connector CN8 2.18 4P Power Connector CN9Signal Signal2.19 TV-Out Connector CN10 2.20 DVI Connector CN112.21 Audio Input/Output Connector CN12 Signal2.22 Ethernet 10/100Base-TX RJ-45 Phone Jack Connector CN13 2.23 External 5VSB/PWRGD Connector CN142.24 IrDA Connector CN15 Signal2.25 Fan Connector CN16 2.26 Mini-DIN PS/2 Connector CN172.27 Serial Port COM1 Connector CN18 PinSignal2.28 CRT Display Connector CN19 2.29 External Battery VBAT22.30 Mini PCI Slot MPCI1 2.31 CompactFlash Disk Slot CFD1SubCompact Board G E N E - 8 3 1Award BIOS Setup Chapter 3 Award BIOS SetupChapter SubCompact BoardSystem configuration verification 3.1 System Test and InitializationEntering Setup Standard CMOS FeaturesAdvanced BIOS Features Advanced Chipset FeaturesPower Management Setup PnP/PCI ConfigurationsLoad Fail-Safe Defaults Load Optimized DefaultsExit Without Saving Set Supervisor/User PasswordSave and Exit Setup Driver Installation Chapter 4 Driver InstallationChapter SubCompact BoardFollow the sequence below to install the drivers 4.1 Installation Chapter4 Drivers InstallationStep 4 - Install Realtek AC97 codec Driver Programming the Watchdog Timer AppendixAppendix A Programming the Watchdog Timer A-1 SubCompact BoardAppendix A Programming the Watchdog Timer A-2 Configuring Sequence DescriptionA.1 Programming 2 Modify the Data of the Registers 1 Enter the MB PnP Mode3 Exit the MB PnP Mode Configure Control Index=02h WatchDog Timer Configuration RegistersAppendix A Programming the Watchdog Timer A-4 SubCompact BoardWatchDog Timer Control Register Index=71h, Default=00h WatchDog Timer Configuration Register Index=72h, Default=00hWatchDog Timer Time-out Value Register Index=73h, Default=00h Appendix A Programming the Watchdog Timer A-5A.2 ITE8712 Watchdog Timer Initial Program game port enable mov cl call SetLogicDevice InitialOK RET ExitConfigurationMode ENDP CheckChip PROC NEAR MOV AL,20h CALL ReadConfigurationData CMP AL,87h JNE NotInitial MOV AL,21hCALL ReadConfigurationData CMP AL,12h JNE NotInitial NeedInitial STC RET NotInitial CLC RET CheckChip ENDP ReadConfigurationData PROC NEARMOV DX,WORD PTR CSCfgPort+06h IN AL,DX RET ReadConfigurationData ENDP END Main Appendix A Programming the Watchdog Timer A-10SetLogicDevice proc near push ax push cx xchg al,cl mov cl,07h call SuperioSetReg pop cx pop ax ret SetLogicDevice endpI/O Information AppendixSubCompact Board G E N E - 8 3 1B.1 I/O Address Map B.2 1st MB Memory Address MapSubCompact BoardG E N E - 8 3 1 Appendix B I/O Information B-2B.3 IRQ Mapping Chart B.4 DMA Channel AssignmentsSubCompact BoardG E N E - 8 3 1 Appendix B I/O Informaion B-3