6 Channel Audio & Mini PCI
GENE-8310
Intel Celeron M Processor Subcompact Board With LVDS, Ethernet
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Copyright Notice
Acknowledgments
Packing List
Contents
Chapter 2 Quick Installation Guide
Chapter 1 General Information
Chapter 3 Award BIOS Setup
Chapter 4 Driver Installation
Appendix A Programming The Watchdog Timer
IRQ Mapping Chart
Appendix B
I/O Information
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General Information
Chapter
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Multiple Display Modes
Superb Performance and Controllable Power Usage
1.1 Introduction
Chapter 1 General Information
Wide Expansion Capability
AC-97 3D Surround 5.1 Channel Audio
1.2 Features
48-bit Dual Channels LVDS TFT LCD 10/100Mbps Fast Ethernet
Supports Type II CompactFlash Memory
1.3 Specifications
System
Display
support Wake-up function
Two 5 x 2 Pin Headers Support
4 USB 2.0 Ports Does not
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Chapter
Quick Installation Guide
Chapter 2 Quick Installation Guide
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2.1 Safety Precautions
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2.2 Location of Connectors and Jumpers Component Side
Chapter 2 Quick Installation Guide
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Solder Side
Chapter 2 Quick Installation Guide
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Chapter 2 Quick Installation Guide
2.3 Mechanical Drawing
Component Side
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Chapter 2 Quick Installation Guide
Solder Side
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Chapter 2 Quick Installation Guide
Jumpers
2.4 List of Jumpers
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Connectors
2.5 List of Connectors
CN17
Closed
2.6 Setting Jumpers
Open
Closed
2.8 LCD Voltage Selection JP2
2.10 USB2.0 Port 1 Connector CN1
2.7 Clear CMOS Selection JP1
2.9 COM2 RI/+5V Selection JP5
Signal
2.11 USB2.0 Port 2 Connector CN2
2.12 Primary IDE Hard Drive Connector CN3
Signal
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2.13 Digital IO Connector CN4
DIO Address is 801H
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Signal
2.15 Serial Port COM2 Connector CN6
2.14 Front Panel CN5
Signal
Signal
2.16 Parallel Port Connector CN7
Signal
Signal
Signal
2.17 Dual Channel LVDS Connector CN8
2.18 4P Power Connector CN9
Signal
2.21 Audio Input/Output Connector CN12
2.19 TV-Out Connector CN10
2.20 DVI Connector CN11
Signal
2.24 IrDA Connector CN15
2.22 Ethernet 10/100Base-TX RJ-45 Phone Jack Connector CN13
2.23 External 5VSB/PWRGD Connector CN14
Signal
2.27 Serial Port COM1 Connector CN18
2.25 Fan Connector CN16
2.26 Mini-DIN PS/2 Connector CN17
PinSignal
2.30 Mini PCI Slot MPCI1
2.28 CRT Display Connector CN19
2.29 External Battery VBAT2
2.31 CompactFlash Disk Slot CFD1
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Chapter
Award BIOS Setup
Chapter 3 Award BIOS Setup
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System configuration verification
3.1 System Test and Initialization
Advanced BIOS Features
Entering Setup
Standard CMOS Features
Advanced Chipset Features
Load Fail-Safe Defaults
Power Management Setup
PnP/PCI Configurations
Load Optimized Defaults
Set Supervisor/User Password
Save and Exit Setup
Exit Without Saving
Chapter
Driver Installation
Chapter 4 Driver Installation
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Follow the sequence below to install the drivers
4.1 Installation
Chapter4 Drivers Installation
Step 4 - Install Realtek AC97 codec Driver
Appendix A Programming the Watchdog Timer A-1
Programming the Watchdog Timer
Appendix
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Configuring Sequence Description
A.1 Programming
Appendix A Programming the Watchdog Timer A-2
1 Enter the MB PnP Mode
3 Exit the MB PnP Mode
2 Modify the Data of the Registers
Appendix A Programming the Watchdog Timer A-4
Configure Control Index=02h
WatchDog Timer Configuration Registers
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WatchDog Timer Time-out Value Register Index=73h, Default=00h
WatchDog Timer Control Register Index=71h, Default=00h
WatchDog Timer Configuration Register Index=72h, Default=00h
Appendix A Programming the Watchdog Timer A-5
A.2 ITE8712 Watchdog Timer Initial Program
game port enable mov cl call SetLogicDevice InitialOK
CALL ReadConfigurationData CMP AL,12h JNE NotInitial NeedInitial STC
RET ExitConfigurationMode ENDP CheckChip PROC NEAR MOV AL,20h
CALL ReadConfigurationData CMP AL,87h JNE NotInitial MOV AL,21h
RET NotInitial CLC RET CheckChip ENDP ReadConfigurationData PROC NEAR
MOV DX,WORD PTR CSCfgPort+06h IN AL,DX RET ReadConfigurationData ENDP
SetLogicDevice proc near push ax push cx xchg al,cl mov cl,07h
END Main
Appendix A Programming the Watchdog Timer A-10
call SuperioSetReg pop cx pop ax ret SetLogicDevice endp
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I/O Information
Appendix
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B.1 I/O Address Map
B.2 1st MB Memory Address Map
Appendix B I/O Information B-2
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B.3 IRQ Mapping Chart
B.4 DMA Channel Assignments
Appendix B I/O Informaion B-3