Intel 88ENEP3S00 user manual POST Codes, hex Name, Description, Appendix

P3 Series User's Manual

APPENDIX 1

POST Codes

NOTE: EISA POST codes are typically output to port address 300h.

ISA POST codes are output to port address 80h.

Code
(hex) Name		Description
C0 Turn Off Chipset Cache		OEM Specific-Cache control
1	Processor Test 1	Processor Status (1FLAGS) Verification. Tests the following
		processor status flags: carry, zero, sign, overflow, The BIOS
		sets each flag, verifies they are set, then turns each flag off
		and verifies it is off.
2	Processor Test 2	Read/Write/Verify all CPU registers except SS, SP, and BP with
		data pattern FF and 00.
3	Initialize Chips	Disable NMI, PIE, AIE, UEI, SQWV Disable video, parity
		checking, DMA Reset math coprocessor. Clear all page
		registers, CMOS shutdown byte. Initialize timer 0, 1, and 2,
		including set EISA timer to a known state. Initialize DMA
		controllers 0 and 1. Initialize interrupt controllers 0 and 1.
		Initialize EISA extended registers.
4	Test Memory Refresh	RAM must be periodically refreshed to keep the memory from
	Toggle	decaying. This function ensures that the memory refresh
		function is working properly.
5	Blank video, Initialize	Keyboard controller initialization.
	keyboard
6	Reserved
7	Test CMOS Interface and	Verifies CMOS is working correctly, detects bad battery.
	Battery Status
BE	Chipset Default	Program chipset registers with power on BIOS defaults.
	Initialization
C1	Memory presence test	OEM Specific-Test to size on-board memory.
C5	Early Shadow	OEM Specific-Early Shadow enable for fast boot.
C6	Cache presence test	External cache size detection.
8	Setup low memory	Early chip set initialization. Memory presence test OEM chip
		set routines. Clear low 64K of memory. Test first 64K memory.

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