Return to Section TOC
Return to Section TOC
Return to Master TOC
Return to Master TOC
TROUBLESHOOTING & REPAIR | ||||||
| INVERTER BOARD RESISTANCE TEST (CONTINUED) |
| ||||
| FIGURE F.6 – INVERTER BOARD TEST POINTS |
| ||||
| Collector |
|
|
|
|
|
| Gate Emitter | IGBT |
|
| ||
| Channel A | Channel A |
|
| ||
|
|
|
|
|
|
|
INVERTER BOARD
|
|
|
|
|
Collector | Emitter | Gate | IGBT |
|
channel B | ||||
Channel B |
|
|
|
|
Return to Section TOC
to Section TOC
Return to Master TOC
to Master TOC
PROCEDURE
1. Disconnect power to the INVERTEC® V155-S.
2. Perform the Case Cover Removal Procedure.
3. Perform the Input Filter Capacitor Discharge
4. VisuallyProcedurecheck for burned areas on both sides of the Inverter Board. If no obvious damage is evident, continue to Step 5.
Note: The following tests may be performed without
5. Check the IGBTʼs for “shorts” using the volt/ohmmeter in the diode test position, check each IGBT from emitter to collector. See Figure F.6.
Note: Normal value is approximately 0.40 VDC in one polarity and a charging value in the opposite polarity.
The IGBTʼs of each channel are connected in par- allel so it is only necessary to check one Emitter to Collector of each channel.
6. Check each device from gate to emitter. See Figure F.6
Note: Normal value is approximately .5VDC in both polarities.
Note: Actual readings will vary depending on the meter being used. Similar tests on all devices should give similar results.
These devices will usually fail “shorted” resulting in a zero or very low resistance reading from Emitter to Collector. If they “open” physical dam- age should be evident.
Return
Return
