MiTAC 8355 service manual VT8235 South Bridge-3, PCI Bus Interface Continue

8355 N/B MAINTENANCE

5.3 VT8235 South Bridge-3

PCI Bus Interface

Signal Name	Pin #	I/O	Signal Description
AD[31:0]	see pin	IO	Address /Data Bus. Multiplexed address and data. The address is
	list)		driven with FRAME# assertion and data is driven or received in
			following cycles.
CBE[3:0]#	L1,A4,	IO	Command /Byte Enable. The command is driven with FRAME#
	D1,F4		assertion. Byte enables corresponding to supplied or requested data
			are driven on following clocks.
DEVSEL#	B3	IO	Device Select. The VT8235 asserts his signal o claim PCI transactions
			through positive or subtractive decoding. As an input, DEVSEL#
			indicates the response to a VT8235-initiated transaction and is also
			sampled when decoding whether to subtractively decode the cycle.
FRAME#	B4	IO	Frame. Assertion indicates the address phase of a PCI transfer.
			Negation indicates that one more data transfer is desired by the cycle
			initiator.
IRDY#	C4	IO	Initiator Ready. Asserted when the initiator is ready for data transfer.
TRDY#	A3	IO	Target Ready. Asserted when the target is ready for data transfer.
STOP#	C3	IO	Stop. Asserted by the target to request the master to stop the current
			transaction.
SERR#	C1	I	System Error. SERR# can be pulsed active by any PCI device that
			detects a system error condition. Upon sampling SERR# active, the
			VT8235 can be programmed o generate an NMI to the CPU.
PAR	D3	IO	Parity. A single parity bi is provided over AD[31:0]and C/BE[3:0]#.
INTA#	P1,	I	PCI Interrupt Request .The INTA# through INTD# pins are typically
INTB#	P2,		connected to the PCI bus INTA#-INTD# pins per the able below.
INTC#	P3,		INTE-H# are enabled by setting Device 17,Function 0 Rx5B[1]=1.
INTD#	R1		BIOS settings must match the physical connection method.
INTE#	A7,
/GPIO12	B8,
/PCGNTA,	D8,				INTB#	INTC#	INTD#
INTF#	C7			INTA#
			PCI Slot 1	INTA#	INTB#	INTC#	INTD#
/GPIO13
			PCI Slot 2	INTB#	INTC#	INTD#	INTE#
/PCGNTB,
			PCI Slot 3	INTC#	INTD#	INTE#	INTF#
INTG#
			PCI Slot 4	INTD#	INTE#	INTF#	INTG#
/GPIO14,			PCI Slot 5	INTE#	INTF#	INTG#	INTH#
INTH#			PCI Slot 6	INTF#	INTG#	INTH#	INTA#
/GPIO15

PCI Bus Interface Continue

Signal Name	Pin #	I/O	Signal Description
REQ5#/GPI7,	N4	I	PCI Request. These signals connect to the VT8235 from each PCI slot
REQ4#,	L4		(or each PCI master)o request he PCI bus. To use pin N4 as REQ5#,
REQ3#,	H4		Function 0 RxE4 must be set to 1 otherwise his pin will function as
REQ2#,	D4		General Purpose Input 7.
REQ1#,	C5
REQ0#	D6
GNT5#/GPO	P4	O	PCI Grant. These signals are driven by he VT8235 to grant PCI access
7,	M4		to a specific PCI master. To use pin P4 as GNT5#,Function 0 RxE4
GNT4#,	J4		must be set to 1 otherwise this pin will function as General Purpose
GNT3#,	E4		Output 7.
GNT2#,	D5
GNT1#,	E6
GNT0#
PCIRST#	R2	O	PCI Reset. This signal is used o reset devices attached to the PCI bus.
PCICLK	R22	I	PCI Clock. This signal provides timing for all transactions on the PCI
			Bus.
PCKRUN#	AF5	IO	PCI Bus Clock Run. This signal indicates whether he PCI clock is or
			will be stopped high) or running (low).The VT8235 drives his signal
			low when he PCI clock is running default on reset)and releases it
			when it stops the PCI clock. External devices may assert this signal
			low o request hat he PCI clock be restarted or prevent it from
			stopping. Connect his pin o ground using a 100 .resistor if he function
			is not used. Refer to the“PCI Mobile Design Guide”and he VIA
			“VT8633 Apollo Pro266 Design Guide”for more details.

PC /PCI DMA

Signal Name	Pin #	I/O	PU	Signal Description
PCREQA/GPIO8/VGA	C8	I		PC /PCI Request A. Device 17 Function 0 Rx53[7]=1
TE
PCREQB /GPIO9	B7	I		PC /PCI Request B. Device 17 Function 0 Rx53[7]=1
PCGNTA /GPIO12	A7	O		PC /PCI Grant A. Device 17 Function 0 Rx53[7]=1
PCGNTB /GPIO13	B8	O		PC /PCI Grant B. Device 17 Function 0 Rx53[7]=1

108