8355 N/B MAINTENANCE

5.3 VT8235 South Bridge-7

Power Management and Event Detection

Signal Name

Pin #

I/O

Signal Description

PWRBTN#

AD2

I

Power Button.Used by the Power Management

 

 

 

subsystem to monitor an external system on/off but

 

 

 

on or switch. Internal logic powered by VSUS33.

SLPBTN#/GPIO21

V1

I

Sleep Button. Used by he Power Management

/ACSDIN3 /PCS1#

 

 

subsystem to monitor an external sleep but on or

 

 

 

switch.RxE4[6]=1,80[6]=1,E5[2]=0 and PMIO

 

 

 

Rx4C[21]=1

RSMRST#

AD5

I

Resume Reset. Resets he internal logic connected o

 

 

 

he VSUS33 power plane and also resets portions of

 

 

 

he internal RTC logic. Internal logic powered by

 

 

 

VBAT.

EXTSMI#/GPI2

AA1

IOD

External System Management Interrupt. When

 

 

 

enabled o allow it ,a falling edge on this input causes

 

 

 

an SMI# to be generated o he CPU o enter SMI

 

 

 

mode.(10K PU to VSUS33 if not used)(3.3V only)

PME#

W3

I

Power Management Event.(10K PU o VSUS33 if

 

 

 

not used)

SMBALRT#

AB2

I

SMB Alert .When programmed to allow it (SMB I/O

 

 

 

Rx8[3]=1),assertion generates an IRQ, SMI,or power

 

 

 

management event.(10K PU o VSUS33 if not used)

LID#/GPI4

AC1

I

Notebook Computer Display Lid Open /Closed

 

 

 

Monitor. Used by he Power Management subsystem

 

 

 

to monitor he opening and closing of the display lid

 

 

 

of notebook computers. Can be used o detect either

 

 

 

low-to-high or high-to-low transitions o generate an

 

 

 

SMI#.(10K PU o VSUS33 if not used)

INTRUDER#/GPI16

AD3

I

Intrusion Indicator. The value of his bi may be read at

 

 

 

PMIO Rx20[6]

THRM#/GPI18

Y4

I

Thermal Alarm Monitor.Rx8C[3]=1.Rising or

/AOLGPI

 

 

falling edges (selectable by PMIO Rx2C[6])may be

 

 

 

detected to status at used a PMIO Rx20[10].Setting of

 

 

 

this status bit may then be used to generate an SCI or

 

 

 

SMI. THRM# may also be used to enable duty cycle

 

 

 

control of stop-clock (STPCLK#)o automatically

 

 

 

limit maximum temperature (see Device 17 Function

 

 

 

0 Rx8C[7-3]).

RING#/GPI3

Y2

I

Ring Indicator. May be connected to external

 

 

 

modem circuitry to allow he system to be re-activated

 

 

 

by a received phone call.(10K PU to VSUS33 if not

 

 

 

used)

BATLOW#/GPI5

W4

I

Battery Low Indicator. (10K PU to VSUS33 if not

 

 

 

used)(3.3V only)

Power Management and Event Detection Continue

Signal Name

Pin #

I/O

Signal Description

CPUSTP#/GPO5

AC7

O

CPU Clock Stop (RxE4[0]=0).Signals the system

 

 

 

clock generator to disable the CPU clock outputs. Not

 

 

 

connected if not used.

PCISTP#/GPO6

AF6

O

PCI Clock Stop (RxE4[1]=0).Signals the system

 

 

 

clock generator o disable he PCI clock outputs. Not

 

 

 

connected if not used.

SUSA#/GPO1

AA2

O

Suspend Plane A Control (Rx94[2]=0).Asserted

 

 

 

during power management POS, STR, and STD

 

 

 

suspend states. Used to control the primary power

 

 

 

plane.(10K PU to VSUS33 if not used)

SUSB#/GPO2

AF2

O

Suspend Plane B Control (Rx94[3]=0).Asserted

 

 

 

during power management STR and STD suspend

 

 

 

states. Used o control he secondary power plane.(10K

 

 

 

PU o VSUS33 if not used)

SUSC#

AF1

O

Suspend Plane C Control. Asserted during power

 

 

 

management STD suspend state. Used to control he

 

 

 

tertiary power plane. Also connected to ATX

 

 

 

power-on circuitry. (10K PU o VSUS33 if not used)

SUSST1#/GPO3

Y3

O

Suspend Status 1 (Rx94[4]=0).Typically connected

 

 

 

to the North Bridge to provide information on host

 

 

 

clock status. Asserted when the system may stop the

 

 

 

host clock, such as Stop Clock or during POS, STR,

 

 

 

or STD suspend statues. Connect 10K PU to

 

 

 

VSUS33.

SUSCLK

AB1

O

Suspend Clock.32.768 KHz output clock for use by

 

 

 

the North Bridge (e.g.,VT8633 or VT8366)for

 

 

 

DRAM refresh purposes. Stopped during

 

 

 

Suspend-to-Disk and Soft-Off modes. Connect 10K

 

 

 

PU to VSUS33.

CPUMISS /GPI17

Y1

I

CPU Missing. Used to detect the physical presence

 

 

 

of the CPU chip in its socket. High indicates no CPU

 

 

 

present. Connect to he CPUMISS pin of the CPU

 

 

 

socket.The state of his pin may be read in the SMBus

 

 

 

2 registers.This pin may be used as CPUMISS and

 

 

 

GPI17 a the same time.

AOLGPI /GPI18

R2

I

Alert On LAN. The state of this pin may be read in

/THRM#

 

 

the SMBus 2 registers. This pin may be used as

 

 

 

AOLGPI, GPI18andTHRM#alla the same time.

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MiTAC 8355 service manual VT8235 South Bridge-7, Power Management and Event Detection Continue