8355 N/B MAINTENANCE

•Arbitrated short reset

•Enhanced priority arbitration

•Connection debounce

•Multispeed packet concatenation

•Ack accelerated arbitration

•Fly-by concatenation

•Per port disable, suspend, resume, through register write and remote command packet

•Remote access packet

•Boundary node short reset

•No PHY_ID wrap past 63

Logic performs bus initialization and arbitration functions

Encode and decode functions included for data-strobe bit-level encoding

Incoming data resynchronized to local clock.

24.576 MHz crystal oscillator and PLL provide TX/RX data at 100/200/400 Mbps and Link-Layer Controller clock at 49.152 MHz.

Cable power presence monitoring.

Programmable node power class information for system power management

Fully Compliant 1394a P2000 PHY register map

Separate TPBIAS for each port

Cable ports monitor line conditions for active connection to remote node

Automatic power down inactive circuit and logic for low power application

Self power up reset and pinless PLL to reduce passive component counts on system

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MiTAC service manual 8355 N/B Maintenance