SPI bus consists of five signal lines. Refer to Appendix Table 1 for the signal information. A communications failure between the host processor and the Secure Module will be indicated as an “ERROR 09/ 10” message on the radio display.

UNSW B+

Vdd

12

SPI CLK

17

18

SPI TX DATA (MOSI)

21

EXP SEL 1

3

2.1MHz REF CLK

 

ASFIC PRE-EMP out

7

10

DISCRIMINATOR

 

DVP WE

16

15

KEY INSERT DATA

13

KEY/FAIL

12

RESET

 

Interface and Control

Serial Peripheral Interface (SPI)

Encode / Decode

Key Variable Storage

4 11

19SPI RX DATA (MISO)

20EXP INT 1

14

TX AUDIO

 

9AUX RX

24 CONT 5V

Not Connected: 5,6,8,22,23,25

Appendix Figure 1. Secure Module

MAEPF-26127-O

Appendix A Table 1. MTS 2000 Single Key Secure Module I/O Definition

SIGNAL NAME

CONNECTOR PLUG

FUNCTION

P1 PIN NUMBER

 

 

 

 

 

 

 

 

UNSW B+

1

Unswitched battery voltage

 

 

 

Vdd

2

Switched 5 volt supply

 

 

 

2.1MHz REF CLK

3

2.1/2.4 MHz clock signal

 

 

 

GROUND

4

Ground

 

 

 

ASFIC PRE-EMP out

7

Transmit Clear Audio

 

 

 

AUX RX

9

Receive Clear Audio

 

 

 

DISCRIMINATOR

10

Receive Encrypted Audio

 

 

 

GROUND

11

Ground

 

 

 

RESET

12

Radio Reset - Does NOT reset module

 

 

 

KEY/FAIL

13

Keyloading Signal

 

 

 

TX AUDIO

14

Transmit Encrypted Audio

 

 

 

KEY INSERT DATA

15

Keyloading Signal

 

 

 

DVP WE

16

Keyloading Signal

 

 

 

SPI CLK

17

SPI Data Clock

 

 

 

SPI TX DATA (MOSI)

18

SPI Data from Host

 

 

 

SPI RX DATA (MISO)

19

SPI Data to Host

 

 

 

EXP INT1

20

SPI Secure Interrupt Request

 

 

 

EXP SEL1

21

SPI Secure Slave Select

 

 

 

CONT 5V

24

Continuous 5 Volt Regulator Output (Not Used)

 

 

 

 

5,6,8,22,23,25

Not Used

 

 

 

Appendix A- 2

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Image 140
Motorola HT 1000 service manual Appendix . Secure Module, Signal Name Connector Plug Function P1 PIN Number