BIOS Setup
▶CH1/ CH2/ CH3 or
This controls the CAS latency, which determines the timing delay (in clock cycles) before SDRAM starts a read command after receiving it.
▶CH1/ CH2/ CH3 or
When DRAM is refreshed, both rows and columns are addressed separately. This setup item allows you to determine the timing of the transition from RAS (row ad- dress strobe) to CAS (column address strobe). The less the clock cycles, the faster the DRAM performance.
▶CH1/ CH2/ CH3 or
This setting controls the number of cycles for Row Address Strobe (RAS) to be allowed to precharge. If insufficient time is allowed for the RAS to accumulate its charge before DRAM refresh, refresh may be incomplete and DRAM may fail to retain data. This item applies only when synchronous DRAM is installed in the sys- tem.
▶CH1/ CH2/ CH3 or
This setting determines the time RAS takes to read from and write to memory cell.
▶CH1/ CH2/ CH3 or
This setting determines the time RFC takes to read from and write to a memory cell.
▶CH1/ CH2/ CH3 or
Minimum time interval between end of write data burst and the start of a precharge command. Allows sense amplifiers to restore data to cells.
▶CH1/ CH2/ CH3 or
Minimum time interval between the end of write data burst and the start of a col-
▶CH1/ CH2/ CH3 or
Specifies the
▶CH1/ CH2/ CH3 or
Time interval between a read and a precharge command. ▶CH1/ CH2/ CH3 or
This item is used to set the tFAW timing.
▶Current CH1/ CH2/ CH3 or
These item show the advanced DRAM timings.
▶Channel 1/ Channel 2/ Channel 3 or Channel
Setting to [Auto] enables the advance memory timing automatically to be determined by BIOS. Setting to [Manual] allows you to set the following advanced memory tim- ings.