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Omega Speaker Systems PCI-DAS1001, PCI-DAS1002 manual 8254B Control Register, BADR3 + Bh

Models: PCI-DAS1001 PCI-DAS1002

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8254B CONTROL REGISTER

BADR3 + Bh

WRITE ONLY

7	6	5	4	2	3	1	0

D7	D6	D5	D4	D3	D2	D1	D0

The control register is used to set the operating Modes of 8254B Counters 0,1 & 2. A counter is configured by writing the correct Mode information to the Control Register, then the proper count data must be written to the specific Counter Regis- ter.

The Counters on the 8254 are 16-bit devices. Since the interface to the 8254 is only 8-bits wide, Count data is written to the Counter Register as two successive bytes. First the low byte is written, then the high byte. The Control Register is 8-bits

wide. Further information can be obtained on the 8254 data sheet, available from Intel or Harris.

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Omega Speaker Systems PCI-DAS1001, PCI-DAS1002 manual 8254B Control Register, BADR3 + Bh

Contents

Users Guide Table of Contents BADR2 BADR0 BADR1BADR3 BADR4Introduction Introduction InstallationDOS and/or Windows RUN InstaCalHardware Connections Connector PIN DiagramAnalog Connections Single-Ended and Differential InputsSingle-Ended Inputs Differential Inputs Differential InputWhich system do you have? System Grounds and IsolationSystems with Common Mode ground offset Voltages Small Common Mode VoltagesLarge Common Mode Voltages Ground Category Input Configuration Our view PCI-DAS1000 and signal source already have isolated grounds Board Board Programming & Software Applications Analog Inputs SELF-CALIBRATION of the PCI-DAS1000Analog Outputs BADR1 BADR0Interrupt / ADC Fifo Register Region Function OperationsEoaie InteIntcl AdflclCHL8-CHL1, CHH8-CHH1 ADC Channel MUX and Control Register BADR1 +EOC Pacer Source= ADC Done = ADC Busy Trigger CONTROL/STATUS Register BADR1 + TS10ARM C0SRC Fifo Mode Sample CTRXtrig IndxgtBADR1 + Calibration RegisterDAC Channel Cal Function Cal SourceDAC CONTROL/STATUS Register BADR1 + Dacen ModeDACnR10 DACnR1 DACnR0 Range LSB SizeADC Data Register BADR2 + BADR2ADC Fifo Clear Register BADR2 + MSB LSBADC Pacer Clock Data and Control Registers BADR3BADR3 + Device Counter # FunctionDigital I/O Data and Control Registers ADC 8254 Control RegisterDIO Port a Data DIO Port B DataDIO Port C Data DIO Control RegisterPort a Port C Port B Upper Lower OUT 8254B Counter 1 Data User Counter #5 Index and User Counter 4 Data and Control Registers8254B Counter 2 Data User Counter #6 BADR3 + AhBADR3 + Bh 8254B Control Register1 DAC0 Data Register BADR4BADR4 + 2 DAC1 Data RegisterElectrical Specifications Analog Output Environmental Power consumptionEC Declaration of Conformity