| 7.0  | 17 | 
| 7.1 REGISTER OVERVIEW | 17 | 
| 7.2 BADR0 | 17 | 
| 7.3 BADR1 | 17 | 
| 7.3.1 INTERRUPT / ADC FIFO REGISTER | 17 | 
| 7.3.2 ADC CHANNEL MUX AND CONTROL REGISTER | 19 | 
| 7.3.3 TRIGGER CONTROL/STATUS REGISTER | 21 | 
| 7.3.4 CALIBRATION REGISTER | 23 | 
| 7.3.5 DAC CONTROL/STATUS REGISTER | 24 | 
| 7.4 BADR2 | 25 | 
| 7.4.1 ADC DATA REGISTER | 25 | 
| 7.4.2 ADC FIFO CLEAR REGISTER | 25 | 
| 7.5 BADR3 | 26 | 
| 7.5.1 ADC PACER CLOCK DATA AND CONTROL REGISTERS | 26 | 
| 7.5.2 DIGITAL I/O DATA AND CONTROL REGISTERS | 27 | 
| 7.5.3 INDEX AND USER COUNTER 4 DATA AND CONTROL REGISTERS . 29 | |
| 7.6 BADR4 | 31 | 
| 7.6.1 DAC0 DATA REGISTER | 31 | 
| 7.6.2 DAC1 DATA REGISTER | 31 | 
| 8.0 ELECTRICAL SPECIFICATIONS | 32 | 
| 8.1 ANALOG INPUT SECTION | 32 | 
| 8.2 ANALOG OUTPUT | 33 | 
| 8.3 PARAELLEL DIGITAL INPUT/OUTPUT | 33 | 
| 8.4 COUNTER SECTION | 34 | 
| 8.5 OTHER SPECIFICATIONS | 34 | 
