PLAR3idle

3. Configuration Options

Table 3-23. Signaling and Trunk Conditioning Values (3 of 3)

Network Side	Meanings	DSX-1 Side

PLAR3idle	The signaling bits transmitted to the cross-connected	PLAR3idle
	T1 interface during a CGA represent the idle state for
	a PLAR D3 interface (ABCD = 0000).

PLAR3busy	The signaling bits transmitted to the cross-connected	PLAR3busy
	T1 interface during a CGA represent the busy state
	for an PLAR D3 interface (ABCD = 1111).

PLAR4idle	The signaling bits transmitted to the cross-connected	PLAR4idle
	T1 interface during a CGA represent the idle state for
	a PLAR D4 interface (ABCD = 1111).

PLAR4busy	The signaling bits transmitted to the cross-connected	PLAR4busy
	T1 interface during a CGA represent the busy state
	for an PLAR D4 interface (ABCD = 0000).

DPO-idle	The signaling bits transmitted to the cross-connected	DPT-idle
	T1 interface during a CGA represent the idle state for
	a DPO interface (ABCD = 0000).

DPO-busy	The signaling bits transmitted to the cross-connected	DPT-busy
	T1 interface during a CGA represent the busy state
	for a DPO interface (ABCD = 1111).

DPT-idle	The signaling bits transmitted to the cross-connected	DPO-idle
	T1 interface during a CGA represent the idle state for
	a DPT interface (ABCD = 0000).

DPT-busy	The signaling bits transmitted to the cross-connected	DPO-busy
	T1 interface during a CGA represent the busy state
	for a DPT interface (ABCD = 1111).

USER-xxxx	The signaling bits transmitted to the cross-connected	USER-xxxx*
	T1 interface during a CGA represent a user-defined
	pattern of ABCD = xxxx.

* xxxx is the same value on both the Network and the DSX-1 sides.

9000-A2-GB31-00

December 2002

3-57

and 9820-45M, 9123, 9623, 9783, 9720 specifications

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Paradyne 9123, and 9820-45M, 9820-2M, 9820-8M, 9623, 9788, 9128 standalone, 9720, 9783 manual PLAR3idle

Models: and 9820-45M 9123 9623 9783 9720 9820-2M 9128 carrier-mount 9128 standalone 9788 9820-8M

3. Configuration Options

and 9820-45M, 9123, 9623, 9783, 9720 specifications