Scsi bus phases overview, BUS Free phase | Seagate Ultra 160

3.0Logical characteristics

The operations of the SCSI bus as described in this section are supported by the drive as specified in each individual drive’s Product Manual. The drive always functions as the target unless otherwise stated.

3.1SCSI bus phases overview

The drive responds to the following phases:

BUS FREE phase

ARBITRATION phase

SELECTION phase

RESELECTION phase

COMMAND phase

Data (IN and OUT)

These phases are collectively termed the Information transfer phases

STATUS (IN only)

MESSAGE (IN and OUT)

The COMMAND, DATA, STATUS, and MESSAGE phases are collectively called the information transfer phases.

The SCSI bus can never be in more than one phase at a time. Signals that are not mentioned in a particular context shall not be asserted.

3.1.1BUS FREE phase

The BUS FREE phase indicates that there is no current task and that the SCSI bus is available for a physical connection or physical reconnection. SCSI devices shall detect the BUS FREE phase after the SEL and BSY signals are both false for at least one bus settle delay.

SCSI devices shall release all SCSI bus signals within one bus clear delay after BSY and SEL are continuously negated (false) for one bus settle delay. If a SCSI device requires more than one bus settle delay to detect the BUS FREE phase, it shall release all SCSI bus signals within one bus clear delay minus the excess time to detect the BUS FREE phase. The total time to clear the SCSI bus shall not exceed one bus settle delay plus one bus clear delay.

During normal operation a SCSI target port enters the BUS FREE phase when it releases the BSY signal.

3.1.1.1Unexpected and expected bus free phases

In some cases a SCSI target port (connected to a SCSI initiator port) unexpectedly reverts to the BUS FREE phase to indicate an error condition that it has no other way to handle. This is called an unexpected disconnect.

SCSI target ports shall create a BUS FREE phases after any of the following:

Parallel SCSI Interface Product Manual, Rev. A

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Seagate Ultra 160, Ultra 320 manual Scsi bus phases overview, BUS Free phase, Unexpected and expected bus free phases

Contents

Parallel Scsi Interface Page Parallel Scsi Interface Page Revision Date Writer/Engineer Revision status summary sheet Parallel Scsi Interface Product Manual, Rev. a Table of Contents Parallel Scsi Interface Product Manual, Rev. a Wide transfer Logical characteristics Message system specification SPI information units Miscellaneous Scsi bus characteristicsScsi commands Drive features List of Figures Xii Parallel Scsi Interface Product Manual, Rev. a Interface requirements How to use this interface manual Scope of Scsi standards Applicable standards General interface description Scsi client-server model GlossaryPage Page Page Page Page Page Keywords Message Name Hex Code Number Physical interface characteristicsSummary of Scsi messages Scsi bus Priority Scsi IDs and associated Scsi bus arbitration priorities Scsi bus signals overview Scsi target usage of Pcrca Pcrc signal usage requirements Signal values Signal statesSE signals LVD signals Voltage and current definitions OR-tied signals Signal sources Signal sourcesData bit P cable Data bit a cable I/O DB15-8 Scsi bus phase DB7-0 Scsi bus control timing values in nanoseconds Scsi bus timingTiming Reference Type Value ns Unless Timing description Timing values for negotiated transfer rate Scsi bus data and information phase ST timing valuesNanoseconds unless otherwise noted Timing values for negotiated transfer rate in nanosecondsPage ATN transmit setup time Min Receive Scsi bus data and information phase DT timing values Interconnect and system margin Total transmitter error budget Receiver errorsFast-160 Fast-320 Comments ATN receive setup time ATN transmit setup timeCrosstalk time shift ISI of data Bus free delay Bus clear delayBus set delay Bus settle delay Flow control transmit setup time Flow control receive setup timePCRC receive setup time PCRC transmit setup time Physical disconnection delay Data release delayPower on to selection QAS arbitration delay Receive setup time Receive internal setup timeReceive internal hold time Receive negation period Reset hold time Reset delayReset to selection Residual skew error Skew correction range System deskew delayStrobe offset tolerance System noise at launch Measurement points LVD measurement points Clocking methods for data transfers ST latching data vs. DT latching data DT synchronous transfer example Paced transfer on a Scsi bus Asynchronous transfers Data transfer modesSynchronous transfers Paced transfers DT Data phase parallel transfers ST Data phase parallel transfersData group transfers Information unit transfers Negotiation algorithm Negotiation Negotiable fields When to negotiateNegotiable fields and effects of successful negotiation Negotiation message pair Field name Field Name Message Numerically Responding message requirementsResponse shall be Transfer agreements Transfer period factor relationships Transfer period factorValue Description Message Transfer rate Synchronous Transfer width exponent 12.6 REQ/ACK offset Iureq Protocol optionsProtocol options bits Sdtr negotiation PPR negotiation setting Iureq to one Bus phases resulting from Iureq changesPPR negotiation setting Iureq to zero PPR negotiation keeping Iureq set to zero Rdstrm WrflowRTI Retain Training Information Pcompen Transfer Period Negotiable field combinationsTransfer Negotiation message sequences Message restrictions Parallel Scsi Interface Product Manual, Rev. a Unexpected and expected bus free phases Scsi bus phases overviewBUS Free phase Arbitration and QAS overview Expected bus free phases Normal Arbitration phase QAS protocol QAS phase overview Selection phase Selection overview Information unit transfers disabledInformation unit transfers enabled Selection using attention condition timeout procedure Physical reconnection Reselection phaseReselection phase overview Scsi bus fairness Physical reconnection timeout procedure Signal Phase Direction of transfer Comment Information transfer phasesInformation transfer phases ST synchronous data transfer Asynchronous transferSynchronous transfer Information unit transfer DT synchronous transferPage Data group data field transfer Page Page Page Paced transfer training pattern Paced transfer Start of section B DT Data in phase training patternStart of section a Start of section C DT Data OUT phase training pattern 3.2 P1 data valid/invalid state transitions Starting pacing transfers with no training pattern Starting pacing transfers at end of training pattern Paced information unit transfer Ending pacing transfers Wide transfer Deskewing Data phase Command phase Message phase Status phase Message in phase exception condition handling Signal restrictions between phasesMessage OUT phase Message OUT phase exception condition handling Scsi bus phase sequences overview Scsi bus phase sequences Hard reset or protocol error Reselection Selection Arbitration DT Data Message OUT Parity checking rules for Selection and Reselection phases ST data bus protection using parityData bus protection Data bus protection overview Order of bytes in the CRC field Error detection capabilities Message formats General message protocols and formats One-byte messages Message formatTwo-byte messages Extended messages Link Control Messages Link Control message codes Message categoriesExtended Message Codes Key Identify DisconnectIdentify message format Bit Byte Ignore Wide Residue message format Ignore Wide ResidueIgnore field definition Invalid data bits Linked Command Complete Initiator Detected ErrorMessage Parity Error Message Reject Modify Bidirectional Data Pointer Modify Data Pointer message format No Operation Modify Bidirectional Data Pointer message format Parallel Protocol Request message format Parallel Protocol Request Value 00h 01h-FEh FFh Description Timing values Use QAS for arbitration Use ST Data in and ST Data OUT phases to transfer dataValid protocol options bit combinations Parallel Protocol Request messages implied agreement Save Data Pointers Restore PointersQAS Request Synchronous Data Transfer Request message format Synchronous Data Transfer Request Sdtr messages implied agreements Task Complete Target initiated Sdtr negotiationInitiator initiated Sdtr negotiation Wide Data Transfer Request message format Wide Data Transfer Request Responding Scsi device Wdtr response Implied agreement Wdtr message implied agreementTarget initiated Wdtr negotiation Task attribute message overview and codes Task attribute messages ACA message format Task attribute message codesACA Auto Contingent Allegiance Ordered Head of Queue Task management message codes Task management message codes Task management messagesAbort Task 0Eh Target Reset Logical Unit ResetAbort Task SET Clear ACA Miscellaneous Scsi bus characteristics Hard reset Bus reset condition Asynchronous condition recovery Reset events Saved pointers Active pointers Incorrect initiator connection Command processing considerations and exception conditionsAsynchronous event notification Unexpected Reselection phase Information unit transfer logical operations SPI information unitsPage Parallel Scsi Interface Product Manual, Rev. a 115 116 Parallel Scsi Interface Product Manual, Rev. a Parallel Scsi Interface Product Manual, Rev. a 117 SPI information units SPI command information unit SPI command information unit Bit Byte Task Management flags Codes Description Task Attribute Codes Description SPI LQ information unit Bit Byte SPI LQ information unit Bidi Direction Codes Type Description SPI LQ information unit typeF0H FFh AllPage SPI data information unit Bit Byte SPI data information unitSPI data stream information unit SPI status data stream information unit Bit Byte Reserved Reserved for FCP SPI status information unitSPI status information unit Bit Byte Packetized Failures field Bit Byte SPI command information unit fields invalidPacketized Failures code Codes Description Task management function not supportedPage 130 Parallel Scsi Interface Product Manual, Rev. a Reserved Command implementation requirementsCommand Descriptor Block CDB Page Fixed and variable length Command Descriptor Block formats Additional CDB Data if required Typical CDB for 12-byte commands Bit ByteTypical CDB for 16-byte commands Bit Byte Additional CDB Length n-7 Typical variable length CDB Bit Byte Operation Code 7FhPage Link b Control field Bit Byte LastNaca a Status Status precedence Single command example Command examples Disconnect example Disconnect example Auto Contingent Allegiance or Contingent Allegiance Timing examples Clearing an Auto Contingent Allegiance condition Overlapped commands Asynchronous Event Reporting Incorrect logical unit selectionSense data Autosense Unit Attention condition Logical unit reset Target hard resetQueued tasks formerly queued I/O processes Untagged task queuing Tagged task queuing Programmable operating definition Parameter rounding Incorrect initiator connection S.M.A.R.T. system Default self-testSelf-test operations Short and extended self-tests Self-test modes Foreground modeBackground mode Device type a Command Reference All device types Exception commands for background self-tests Protection code Self-test mode summaryError detection for asynchronous information phases Word Location Signal Meaning Covered signalsPage Protection code usage Error detection propertiesCode description Protection code transmission Error handlingEnabling protection code checking Disabling protection code checking Case 1-Power off during removal or insertion SPI-3 equivalent term SCSI-2 term SPI-3 to SCSI-2 terminology mappingSPI-3 to SCSI-2 terminology mapping Index Code value reserved Disconnect privilege 148 domain 5, 9 dormant Initiator 3, 6, 14, 131, 140 faulted Multidrop 7 multimode Page Scsi Page Wdtr 40 170 Parallel Scsi Interface Product Manual, Rev. a Page Seagate Technology LLC