Error detection capabilities | Seagate Ultra 320, Ultra 160 instruction

For COMMAND, MESSAGE, and STATUS phases, the DB(P_CRCA) signal shall indicate odd parity for DB(7- 0). The DB(P1) signal shall not be checked.

For ST DATA phases, the DB(P_CRCA) signal shall indicate odd parity for DB(7-0). If 8-bit transfers are enabled, the DB(P1) signal shall not be checked. If 16-bit data transfers are enabled, the DB(P1) signal shall indicate odd parity for DB(15-8). If 16-bit transfers are enabled and the last information byte transferred does not fall on the DB(15-8) signals, DB(P1) shall be valid for whatever data is placed on the bus.

Parity protection is not enabled during DT DATA phases.

3.12.3DT data bus protection using CRC

3.12.3.1DT data bus protection using CRC overview

When pCRC protection or iuCRC protection are enabled, the error detecting code is a 32-bit (four byte) Cyclic Redundancy Check (CRC), referred to as CRC-32. It is also used by several other device I/O standards. Four CRC bytes are transferred with data to increase the reliability of data transfers.

3.12.3.2Error detection capabilities

The CRC detects all single bit errors, any two bits in error, or any combination of errors within a single 32-bit range.

3.12.3.3Order of bytes in the CRC field

Figure 74 of ANSI SCSI Parallel Interface (SPI-5), T10/1525D, shows how transmitted data is used to calculate the CRC and how the CRC information is then transmitted.

82	Parallel SCSI Interface Product Manual, Rev. A

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Seagate Ultra 320, Ultra 160 manual Error detection capabilities, Order of bytes in the CRC field

Contents

Parallel Scsi Interface Page Parallel Scsi Interface Page Revision status summary sheet Revision Date Writer/Engineer Parallel Scsi Interface Product Manual, Rev. a Table of Contents Parallel Scsi Interface Product Manual, Rev. a Logical characteristics Wide transfer Message system specification Miscellaneous Scsi bus characteristics Scsi commandsSPI information units Drive features List of Figures Xii Parallel Scsi Interface Product Manual, Rev. a How to use this interface manual Interface requirements Scope of Scsi standards General interface description Applicable standards Glossary Scsi client-server modelPage Page Page Page Page Page Keywords Physical interface characteristics Summary of Scsi messagesMessage Name Hex Code Number Scsi bus Scsi IDs and associated Scsi bus arbitration priorities Priority Scsi bus signals overview Pcrc signal usage requirements Scsi target usage of Pcrca Signal states Signal valuesSE signals LVD signals OR-tied signals Voltage and current definitions Signal sources Signal sourcesData bit P cable Data bit a cable I/O DB15-8 Scsi bus phase DB7-0 Scsi bus timing Scsi bus control timing values in nanosecondsTiming Reference Type Value ns Unless Timing description Scsi bus data and information phase ST timing values Timing values for negotiated transfer rateNanoseconds unless otherwise noted Timing values for negotiated transfer rate in nanosecondsPage ATN transmit setup time Min Receive Scsi bus data and information phase DT timing values Total transmitter error budget Receiver errors Fast-160 Fast-320 CommentsInterconnect and system margin ATN transmit setup time ATN receive setup timeCrosstalk time shift ISI of data Bus clear delay Bus free delayBus set delay Bus settle delay Flow control receive setup time Flow control transmit setup timePCRC receive setup time PCRC transmit setup time Data release delay Physical disconnection delayPower on to selection QAS arbitration delay Receive internal setup time Receive setup timeReceive internal hold time Receive negation period Reset delay Reset hold timeReset to selection Residual skew error System deskew delay Skew correction rangeStrobe offset tolerance System noise at launch Measurement points Clocking methods for data transfers LVD measurement points ST latching data vs. DT latching data Paced transfer on a Scsi bus DT synchronous transfer example Data transfer modes Asynchronous transfersSynchronous transfers Paced transfers ST Data phase parallel transfers DT Data phase parallel transfersData group transfers Information unit transfers Negotiation Negotiation algorithm When to negotiate Negotiable fieldsNegotiable fields and effects of successful negotiation Negotiation message pair Field name Responding message requirements Response shall beField Name Message Numerically Transfer agreements Transfer period factor Transfer period factor relationshipsValue Description Message Transfer rate Synchronous 12.6 REQ/ACK offset Transfer width exponent Protocol options Protocol options bitsIureq Bus phases resulting from Iureq changes Sdtr negotiation PPR negotiation setting Iureq to onePPR negotiation setting Iureq to zero PPR negotiation keeping Iureq set to zero Wrflow RdstrmRTI Retain Training Information Pcompen Negotiable field combinations TransferTransfer Period Message restrictions Negotiation message sequences Parallel Scsi Interface Product Manual, Rev. a Scsi bus phases overview BUS Free phaseUnexpected and expected bus free phases Expected bus free phases Arbitration and QAS overview Normal Arbitration phase QAS phase overview QAS protocol Selection phase Information unit transfers disabled Information unit transfers enabledSelection overview Selection using attention condition timeout procedure Reselection phase Reselection phase overviewPhysical reconnection Physical reconnection timeout procedure Scsi bus fairness Information transfer phases Information transfer phasesSignal Phase Direction of transfer Comment Asynchronous transfer Synchronous transferST synchronous data transfer DT synchronous transfer Information unit transferPage Data group data field transfer Page Page Page Paced transfer Paced transfer training pattern DT Data in phase training pattern Start of section aStart of section B DT Data OUT phase training pattern Start of section C 3.2 P1 data valid/invalid state transitions Starting pacing transfers at end of training pattern Starting pacing transfers with no training pattern Ending pacing transfers Paced information unit transfer Deskewing Wide transfer Command phase Data phase Status phase Message phase Signal restrictions between phases Message in phase exception condition handlingMessage OUT phase Message OUT phase exception condition handling Scsi bus phase sequences Scsi bus phase sequences overview Hard reset or protocol error Reselection Selection Arbitration DT Data Message OUT ST data bus protection using parity Parity checking rules for Selection and Reselection phasesData bus protection Data bus protection overview Error detection capabilities Order of bytes in the CRC field General message protocols and formats Message formats Message format One-byte messagesTwo-byte messages Extended messages Message categories Extended Message CodesLink Control Messages Link Control message codes Key Disconnect IdentifyIdentify message format Bit Byte Ignore Wide Residue Ignore Wide Residue message formatIgnore field definition Invalid data bits Initiator Detected Error Linked Command CompleteMessage Parity Error Message Reject Modify Data Pointer message format Modify Bidirectional Data Pointer Modify Bidirectional Data Pointer message format No Operation Parallel Protocol Request Parallel Protocol Request message format Value 00h 01h-FEh FFh Description Timing values Use ST Data in and ST Data OUT phases to transfer data Valid protocol options bit combinationsUse QAS for arbitration Parallel Protocol Request messages implied agreement Restore Pointers QAS RequestSave Data Pointers Synchronous Data Transfer Request Synchronous Data Transfer Request message format Sdtr messages implied agreements Target initiated Sdtr negotiation Initiator initiated Sdtr negotiationTask Complete Wide Data Transfer Request Wide Data Transfer Request message format Wdtr message implied agreement Target initiated Wdtr negotiationResponding Scsi device Wdtr response Implied agreement Task attribute messages Task attribute message overview and codes Task attribute message codes ACA Auto Contingent AllegianceACA message format Head of Queue Ordered Task management messages Task management message codes Task management message codesAbort Task 0Eh Logical Unit Reset Target ResetAbort Task SET Clear ACA Miscellaneous Scsi bus characteristics Bus reset condition Hard reset Reset events Asynchronous condition recovery Active pointers Saved pointers Command processing considerations and exception conditions Asynchronous event notificationIncorrect initiator connection Unexpected Reselection phase SPI information units Information unit transfer logical operationsPage Parallel Scsi Interface Product Manual, Rev. a 115 116 Parallel Scsi Interface Product Manual, Rev. a Parallel Scsi Interface Product Manual, Rev. a 117 SPI command information unit SPI information units SPI command information unit Bit Byte Task Attribute Codes Description Task Management flags Codes Description SPI LQ information unit SPI LQ information unit Bit Byte Bidi Direction SPI LQ information unit type Codes Type DescriptionF0H FFh AllPage SPI data information unit SPI data stream information unitSPI data information unit Bit Byte SPI status data stream information unit Bit Byte SPI status information unit SPI status information unit Bit ByteReserved Reserved for FCP SPI command information unit fields invalid Packetized Failures field Bit BytePacketized Failures code Codes Description Task management function not supportedPage 130 Parallel Scsi Interface Product Manual, Rev. a Command implementation requirements Command Descriptor Block CDBReserved Page Fixed and variable length Command Descriptor Block formats Typical CDB for 12-byte commands Bit Byte Typical CDB for 16-byte commands Bit ByteAdditional CDB Data if required Typical variable length CDB Bit Byte Operation Code 7Fh Additional CDB Length n-7Page Control field Bit Byte Last Naca aLink b Status Status precedence Command examples Single command example Disconnect example Disconnect example Timing examples Auto Contingent Allegiance or Contingent Allegiance Overlapped commands Clearing an Auto Contingent Allegiance condition Incorrect logical unit selection Sense dataAsynchronous Event Reporting Autosense Unit Attention condition Target hard reset Logical unit resetQueued tasks formerly queued I/O processes Untagged task queuing Tagged task queuing Parameter rounding Programmable operating definition Incorrect initiator connection Default self-test S.M.A.R.T. systemSelf-test operations Short and extended self-tests Foreground mode Background modeSelf-test modes Exception commands for background self-tests Device type a Command Reference All device types Self-test mode summary Error detection for asynchronous information phasesProtection code Covered signals Word Location Signal MeaningPage Error detection properties Code descriptionProtection code usage Error handling Protection code transmissionEnabling protection code checking Disabling protection code checking Case 1-Power off during removal or insertion SPI-3 to SCSI-2 terminology mapping SPI-3 to SCSI-2 terminology mappingSPI-3 equivalent term SCSI-2 term Index Code value reserved Disconnect privilege 148 domain 5, 9 dormant Initiator 3, 6, 14, 131, 140 faulted Multidrop 7 multimode Page Scsi Page Wdtr 40 170 Parallel Scsi Interface Product Manual, Rev. a Page Seagate Technology LLC