Silicon Image SSD-P08G(I)-3521 manual Tpceio

ATTRIBUTE MEMORY DESCRIPTION AND OPERATION

SSD-PXXX(I)-3521 DATA SHEET

Table 21: Card Information Structure (Continued)

Attribute

Data

7

6

5

4

3

2

1

0

Description of Contents

CIS Function

Offset

86h

27h

R

DI

PI

AI

SI

HV

LV

NV

Nominal voltage only follows

Power parameters

•

R: Reserved

for VCC

• DI: Powerdown current information

• PI: Peak current information

• AI: Average current information

• SI: Static current information

• HV: Maximum voltage information

• LV: Minimum voltage information

• NV: Nominal voltage information

88h

55h

X

Mantissa

Exponent

Nominal voltage = 5V

VCC nominal value

8Ah

4Dh

X

Mantissa

Exponent

VCC nominal 4.5V

VCC minimum value

8Ch

5Dh

X

Mantissa

Exponent

VCC nominal 5.5V

VCC maximum value

8Eh

75h

X

Mantissa

Exponent

Maximum average current over 10ms is

Maximum average

80mA

current

90h

64h

R

S

E

I

O

AddrLine

• S = 1: 16-bit hosts supported

I/O space

• E = 1: 8-bit hosts supported

description field

• IO AddrLine: 4 lines decoded

TPCE_IO

92h

F0h

S

P

L

M

V

B

I

N

• S = 1: Share logic active

Interrupt request

• P = 1: Pulse mode IRQ supported

description structure

• L = 1: Level mode IRQ supported

TPCE_IR

• M = 1: Bit mask of IRQs present

• V = 0: No vender unique IRQ

• B = 0: No bus error IRQ

• I = 0: No IO check IRQ

• N = 0: No NMI

94h

FFh

IR

IR

IR

IR

IR

IR

IR

IR

SiliconSystems recommends the IRQ

Mask extension

Q

Q

Q

Q

Q

Q

Q

Q

level to be routed 0 to 15

byte 1 TPCE_IR

7

6

5

4

3

2

1

0

96h

FFh

IR

IR

IR

IR

IR

IR

IR

IR

SiliconSystems recommends routing to

Mask extension

Q

Q

Q

Q

Q

Q

Q

Q

any normal, maskable IRQ.

byte 2 TPCE_IR

15

14

13

12

11

10

9

8

98h

21h

X

R

P

R

O

A

T

-

• X = 0: No more miscellaneous fields

Miscellaneous

•

R: Reserved

features field

• P = 1: Powerdown supported

TPCE_MI

• RO = 0: Not read only mode

• A = 0: Audio not supported

• T = 0: Single drive

9Ah

1Bh

CISTPL__TABLE_ENTRY

Configuration table entry tuple

Tuple code

9Ch

06h

TPL_LINK

Link length is 6 bytes

Link to next tuple

9Eh

01h

I

D

Configuration Index

Contiguous I/O mapped ATA registers

Configuration table

configuration

index

• I = 0: No Interface byte

Byte TPCE_INDX

• D = 0: No Default entry

• Configuration index = 1

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This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc.

All unauthorized use and/or reproduction is prohibited.

3521P-02DSR PAGE 30 FEBRUARY 2, 2009