ATA COMMAND BLOCK AND SET DESCRIPTION

SSD-PXXX(I)-3521 DATA SHEET

Idle — 97h, E3h

When issued by the host, the device’s internal controller sets the BSY bit, enters the Idle mode, clears the BSY bit, and generates an interrupt. If the sector count is non-zero, it is interpreted as a timer count with each count being 5ms, and the automatic power-down mode is enabled. If the sector count is zero, the automatic power-down mode is disabled.

Table 53: Idle — 97h, E3h

Register

D7

D6

D5

D4

 

D3

D2

 

D1

D0

Feature

 

 

 

 

X

 

 

 

 

 

 

 

 

 

 

Sector Count

 

 

Timer Count (5ms increments)

 

 

 

 

 

 

 

 

 

 

 

 

Sector Number

 

 

 

 

X

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Cylinder Low

 

 

 

 

X

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Cylinder High

 

 

 

 

X

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Drive Head

X

X

X

Drive

 

 

X

 

 

 

 

 

 

 

 

 

 

 

 

Command

 

 

 

97h or E3h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SILICONSYSTEMS PROPRIETARY

This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc.

All unauthorized use and/or reproduction is prohibited.

3521P-02DSR

PAGE 68

FEBRUARY 2, 2009

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Silicon Image SSD-P08G(I)-3521 manual Idle 97h, E3h