Silicon Image SSD-P08G(I)-3521 manual Signal Descriptions, Signal Name Pin Type Description

ELECTRICAL SPECIFICATION				SSD-PXXX(I)-3521 DATA SHEET
SIGNAL DESCRIPTIONS
		Table 8: Signal Descriptions
	Signal Name	Pin	Type	Description
	A10-A0	8, 10, 11,	I	These address lines along with the
		12, 14, 15,		-REG signal are used to select the
		16, 17, 18,		following:
		19, 20		• The I/O port address registers
				within the SiliconDrive CF
				• The memory-mapped port address
				registers within the SiliconDrive CF
				• A byte in the card's information
				structure and its configuration
				control and status registers
	A10-A0			This signal is the same as the PC
	(PC Card I/O			Card Memory Mode signal.
	mode)
	A2-A0	18, 19, 20	I	In true IDE mode, only A[2:0] are used
	(True IDE mode)			to select the one of eight registers in
				the Task File. The remaining address
				lines should be grounded by the host.
	BVD1	46	I/O	This signal is asserted high, because
	(PC Card memory			BVD1 is not supported.
	mode)

-STSCHG

(PC Card I/O mode)

This signal is asserted low to alert the host to changes in the RDY/-BSY and Write Protect states while the I/O interface is configured. This signal’s use is controlled by the Card Configuration and Status register.

-PDIAG		In the true IDE mode, this input/output
(True IDE mode)		is the Pass Diagnostic signal in the
		Master/Slave handshake protocol.
BVD2	45	I/O This signal is asserted high, as BVD2
(PC Card memory		is not supported.
mode)

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3521P-02DSR PAGE 7 FEBRUARY 2, 2009