ATA COMMAND BLOCK AND SET DESCRIPTION

SSD-PXXX(I)-3521 DATA SHEET

Idle Immediate — 95h, E1h

When issued by the host, the device’s internal controller sets the BSY bit, enters Idle Mode, clears the BSY bit, and issues an interrupt. The interrupt is issued whether or not the Idle mode is fully entered.

Table 54: Idle Immediate — 95h, E1h

Register

D7

D6

D5

D4

 

D3

D2

 

D1

D0

Feature

 

 

 

 

X

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Sector Count

 

 

 

 

X

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Sector Number

 

 

 

 

X

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Cylinder Low

 

 

 

 

X

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Cylinder High

 

 

 

 

X

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Drive Head

X

X

X

Drive

 

 

 

X

 

 

 

 

 

 

 

 

 

 

 

Command

 

 

 

95h or E1h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SILICONSYSTEMS PROPRIETARY

This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc.

All unauthorized use and/or reproduction is prohibited.

3521P-02DSR

PAGE 69

FEBRUARY 2, 2009

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Image 79
Silicon Image SSD-P08G(I)-3521 manual Idle Immediate 95h, E1h