Reg# A10 A9A4, Primary Secondary | Silicon Image SSD-P08G(I)-3521

ATA AND TRUE IDE REGISTER DECODING

SSD-PXXX(I)-3521 DATA SHEET

PRIMARY AND SECONDARY I/O MAPPED REGISTER DECODING

Table 32: Primary and Secondary I/O Mapped Register Decoding

Reg#	A10	A9:A4	A9:A4	A3	A2	A1	A0	IORD# = L	IOWR# = L
Reg#	A10	Primary	Secondary	A3	A2	A1	A0	IORD# = L	IOWR# = L

0	X	1Fxh	17xh	0	0	0	0	Even Data	Even Data
								Read	Write

0	X	1Fxh	17xh	0	0	0	1	Error	Feature

0	X	1Fxh	17xh	0	0	1	0	Sector	Sector
								Count	Count

0	X	1Fxh	17xh	0	0	1	1	Sector	Sector
								Number	Number

0	X	1Fxh	17xh	0	1	0	0	Cylinder	Cylinder
								Low	Low

0	X	1Fxh	17xh	0	1	0	1	Cylinder	Cylinder
								High	High

0	X	1Fxh	17xh	0	1	1	0	Drive/Head	Drive/Head

0	X	1Fxh	17xh	0	1	1	1	Status	Command

0	X	3Fxh	37xh	0	1	1	0	Alternate	Device
								Status	Control

0	X	3Fxh	37xh	0	1	1	1	Drive	Reserved
								Address

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3521P-02DSR

PAGE 45

FEBRUARY 2, 2009

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Silicon Image SSD-P08G(I)-3521 manual Primary and Secondary I/O Mapped Register Decoding, Reg# A10 A9A4, Primary Secondary

Contents

Overview Features Added UpdatedRevision History Document No Release Date Changes Table of Contents ATA and True IDE Register Decoding Attribute Memory Description and OperationCommon Memory Description and Operation Space Description and Operation ATA Command Set Related Documentation Sales and Support Part Numbering List of Figures List of Tables SSD-PXXXI-3521 Data Sheet Set Multiple Mode C6h Set Sleep Mode 99h, E6h Physical Dimensions Physical Specifications System Power Requirements Product SpecificationsSystem Performance Reliability SiliconDrive Part# Capacity Service Life GB Written per DayOperational Life Span Environmental Specifications Product Capacity SpecificationsProduct Capacity Number Bytes Sectors Cylinders Heads Track Pin Assignments Electrical Specification IOIS16# IOCS16# GND Signal Name Pin Type Description Signal Descriptions Dasp Spkr Inpack Csel Ground True IDE modeDmarq GND Iord This signal is not used in this mode PC Card memory ModeIowr RDY/-BSY ATA SELIreq Dmack Reset+5V, +3.3V power PC Card memory Mode REG Iordy This signal is the same for all modes PC Card I/O ModeVoltage Sense Signals Wait IOIS16 Symbol Parameter Minimum Maximum UnitsAbsolute Maximum Ratings Capacitance Symbol Parameter Maximum UnitsDC Characteristics Symbol Parameter V ±10% 5V ±10% Units Minimum Maximum Attribute and Common Memory Read Timing Attribute and Common Memory Read Timing Attribute and Common Memory Write Timing Attribute and Common Memory Write Timing O Access Read Timing Access Read Timing O Access Write Timing Access Write Timing True IDE Read/Write Access Timing True IDE Read/Write Access Timing True IDE Multiword DMA Read/Write Access Timing True IDE Multiword DMA Read/Write Access Timing Function REG# CE1# CE2# D158 D70 ModeAttribute Memory Description and Operation Attribute Memory Read Operations Attribute Memory Write Operations Register Operation Addr CE1# Attribute Memory Map Card Information Structure Attribute Data Description of Contents CIS Function Offset Cistplfunce Tpcemi Tpcefs Tpceio Exponent Nominal voltage = VCC nominal value A6h 1Eh IRQ Configuration table entry tuple Tuple code E4h 12h Exponent Nominal voltage = VCC nominal value F0h 4Dh SSD-PXXXI-3521 Data Sheet Card Information Structure Sreset Configuration Option Register 200hBits Description Read Changed SigChg IOis8 PwrDn Int Write Default Value Configuration and Status Register 202h Crdy Pin Placement Register 204hRrdy RFU Copy Number Socket Number Default ValueSocket and Copy Register 206h Read/Write Common Memory Read Operations Common Memory Description and OperationCommon Memory Write Operations O Space Write Operations Function Mode REG# CE1# CE2# A0 IORD# IOWR# D158 D70Space Description and Operation O Space Read Operations Memory-Mapped Register Decoding ATA and True IDE Register DecodingReg# Offset A10 A9A4 OE# = L WE# = L Independent I/O Mode Register Decoding Reg# A10 A9A4 Primary and Secondary I/O Mapped Register DecodingPrimary Secondary CS0# CS1# DA02 DA01 DA00 Task File Register Specification Media Changed MC. Set to Error RegisterTrack 0 Not Found TKONF. Set when the execute drive ATA Registers Byte Feature RegisterOperation Read/Write Sector Count Register Read/Write Sector Count Default Value Logical Block Number bits A07-A00 LBA Addressing Sector Number Register Logical Block Number bits A15-A08 LBA Addressing Cylinder Low Register Logical Block Number bits A23-A16 LBA Addressing Cylinder High Register HS3 HS2 HS1 HS0 Drive/Head RegisterLBA27 LBA26 LBA25 LBA24 DRQ Corr IDX ERR Drive Write Fault DWF. Always set toStatus Register BSY Drdy Operation Read/Write ATA Command Code Command Register Alternate Status Register Srst Device Control RegisterNIEN Device Address Register Read/Write NWTG NHS3 NHS2 NHS1 NHS0 NDS1 NDS0 Default Value Class Command Name Registers Used Code ATA Command Block and SET DescriptionATA Command Block and Set Description ATA Command Set ATA Command Set Check Power Mode 98h, E5h Check Power Mode 98h, E5hRegister Executive Drive Diagnostic 90h Executive Drive Diagnostic 90h Format Track 50h Drive Head Number LBA27-24 Command 50hFormat Track 50h Identify Drive ECh Identify Drive ECh Identify Drive Drive Attribute Data Word Data Default Bytes Data Description Address Identify Drive Drive Attribute Data Identify Drive Drive Attribute Data Idle 97h, E3h Idle 97h, E3h Idle Immediate 95h, E1h Idle Immediate 95h, E1h Initialize Drive Parameters 91h Initialize Drive Parameters 91h Recalibrate 1Xh Drive Command 1XhRecalibrate 1Xh Read Buffer E4h Read Buffer E4h LBA Drive Head Number LBA27-24 Command C8hRead DMA C8h Read DMA C8h Read Multiple C4h Drive Head Number LBA27-24 Command C4hRead Multiple C4h Read Sector 20h, 21h Drive Head Number LBA27-24 Command 20h or 21hRead Sector 20h, 21h Read Long Sectors 22h, 23h Drive Head Number LBA27-24 Command 22h or 23hRead Long Sectors 22h, 23h Read Verify Sectors 40h, 41h Drive Head Number LBA27-24 Command 40h or 41hRead Verify Sectors 40h, 41h Seek 7Xh Drive Head Number LBA27-24 Command 7XhSeek 7Xh Feature Operation Set Features EFhSet Features EFh Set Features’ Attributes Set Multiple Mode C6h Set Multiple Mode C6h Set Sleep Mode 99h, E6h Set Sleep Mode 99h, E6h Standby 96h, E2h Standby 96h, E2h Standby Immediate 94h, E0h Standby Immediate 94h, E0h Write Buffer E8h Write Buffer E8h Write DMA CAh Drive Head NumberLBA27-24 Command CAhWrite DMA CAh Write Multiple C5h Drive Head NumberLBA27-24 Command C5hWrite Multiple C5h Write Sectors 30h, 31h Drive Head Number LBA27-24 Command 30h or 31hWrite Sectors 30h, 31h Write Long Sectors 32h, 33h Drive Head Number LBA27-24 Command 32h or 33hWrite Long Sectors 32h, 33h Erase Sectors C0h Drive Head Number LBA27-24 Command C0hErase Sectors C0h Request Sense 03h Extended Error CodesExtended Error Codes Description Request Sense 03h Translate Sector 87h Drive Head Number LBA27-24 Command 87hTranslate Sector 87h Wear-Level F5h Wear-Level F5h Write Multiple w/o Erase CDh Drive Head Number LBA27-24 Command CDhWrite Multiple w/o Erase CDh Write Sectors w/o Erase 38h Drive Head Number LBA27-24 Command 38hWrite Sectors w/o Erase 38h Write Verify 3Ch Drive Head Number LBA27-24 Command 3ChWrite Verify 3Ch 3521 Sales and SupportPart Numbering Part Numbering Nomenclature Part Number Capacity Part Numbers Sample Label Front Label Standard Back Label with Lot Code Information Related Documentation Related Documentation

Silicon Image SSD-P08G(I)-3521 Primary and Secondary I/O Mapped Register Decoding, Reg# A10 A9A4

Models: SSD-P08G(I)-3521

SSD-PXXX(I)-3521 DATA SHEET

Table 32: Primary and Secondary I/O Mapped Register Decoding

Reg#

A10

A9:A4

IORD# = L

IOWR# = L

Primary

Secondary

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