SUPER MICRO Computer MBDX7DA3O user manual Chipset Overview, Xeon Dual Core Processor Features

Chapter 1: Introduction

1-2 Chipset Overview

Built upon the functionality and the capability of the 5000X (Greencreek) chipset, the X7DA3+ motherboard provides the performance and feature set required for dual processor-based workstations with confi guration options optimized for com- munications, presentation, storage, computation or database applications. The 5000X (Greencreek) chipset supports single or dual Xeon 64-bit dual core processor with front side bus speeds of up to 1.333 GHz. The chipset consists of the 5000X (Greencreek) Memory Controller Hub (MCH), the Enterprise South Bridge 2 (ESB2), and the I/O subsystem (PXH-V).

The 5000X (Greencreek) MCH chipset is designed for symmetric multiprocessing across two independent front side bus interfaces. Each front side bus uses a 64-bit wide, 1.333 GHz data bus that transfers data at 10.7 GB/sec. The MCH chipset con- nects up to 8 Fully Buffered DIMM modules, providing a total of 32.0 GB/s for DDR2 667/533 memory. The MCH chipset also provides one x8 PCI-Express and one x4 ESI interface to the ESB2. In addition, the 5000X (Greencreek) chipset offers a wide range of RAS features, including memory interface ECC, x4/x8 Single Device Data Correction, CRC, parity protection, memory mirroring and memory sparing.

Xeon Dual Core Processor Features

Designed to be used with conjunction of the 5000X (Greencreek) chipset, the Xeon Dual Core Processors provide a feature set as follows:

The Xeon Dual Core Processors

L1 Cache Size: Instruction Cache (32KB/16KB), Data Cache (32KB/24KB)

L2 Cache Size: 2MB (per core)

Data Bus Transfer Rate: 8.5 GB/s

Package: FC-LGA6/FC-LGA4, 771 Lands

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