Texas Instruments MSP430x4xx - page 270

USART Operation: UART Mode

14-13USART Peripheral Interface, UART Mode

Transmit Bit Timing

The timing for each character is the sum of the individual bit timings. By

modulating each bit, the cumulative bit error is reduced. The individual bit error

can be calculated by:

Error [%] +Ǌbaud rate

BRCLK ƪ(j)1) UxBR )S

j

i+0miƫ*(j)1)ǋ 100%

With:

baud rate: Desired baud rate

BRCLK: Input frequency − UCLKI, ACLK, or SMCLK

j: Bit position - 0 for the start bit, 1 for data bit D0, and so on

UxBR: Division factor in registers UxBR1 and UxBR0

For example, the transmit errors for the following conditions are calculated:

Baud rate = 2400

BRCLK = 32,768 Hz (ACLK)

UxBR = 13, since the ideal division factor is 13.65

UxMCTL = 6Bh: m7= 0, m6= 1, m5=1, m4 =0, m3 =1, m2= 0,

m1=1, and m0 =1. The LSB of UxMCTL is used first.

Start bit Error [%] +ǒbaudrate

BRCLK ((0)1) UxBR )1)–1Ǔ 100% +2.54%

Data bit D0 Error [%] +ǒbaud rate

BRCLK ((1)1) UxBR)2)–2Ǔ 100% +5. 08%

Data bit D1 Error [%] +ǒbaud rate

BRCLK ((2)1) UxBR)2)–3Ǔ 100% +0. 29%

Data bit D2 Error [%] +ǒbaud rate

BRCLK ((3)1) UxBR)3)–4Ǔ 100% +2. 83%

Data bit D3 Error [%] +ǒbaud rate

BRCLK ((4)1) UxBR)3)–5Ǔ 100% +*1.95%

Data bit D4 Error [%] +ǒbaud rate

BRCLK ((5)1) UxBR)4)–6Ǔ 100% +0. 59%

Data bit D5 Error [%] +ǒbaud rate

BRCLK ((6)1) UxBR)5)–7Ǔ 100% +3. 13%

Data bit D6 Error [%] +ǒbaud rate

BRCLK ((7)1) UxBR)5)–8Ǔ 100% +*1.66%

Data bit D7 Error [%] +ǒbaud rate

BRCLK ((8)1) UxBR)6)–9Ǔ 100% +0. 88%

Parity bit Error[%] +ǒbaud rat e

BRCLK ((9)1) UxBR )7)–10Ǔ 100% +3.42%

Stop bit 1 Error [%] +ǒbaud rate

BRCLK ((10 )1) UxBR)7)–11Ǔ 100% +*1.37%

The results show the maximum per-bit error to be 5.08% of a BITCLK period.

Contents

Main Page Preface Read This First About This Manual Related Documentation From Texas Instruments FCC Warning Notational Conventions Glossary Register Bit Conventions Register Bit Accessibility and Initial Condition Page Contents Page Page Page Page Page Page Introduction 1.1 Architecture 1.2 Flexible Clock System Figure 11. MSP430 Architecture 1.3 Embedded Emulation 1.4 Address Space Figure 12. Memory Map 1.4.1 Flash/ROM 1.4.2 RAM 1.4.3 Peripheral Modules 1.4.4 Special Function Registers (SFRs) 1.4.5 Memory Organization Figure 13. Bits, Bytes, and Words in a Byte-Organized Memory Page 2.1 System Reset and Initialization Figure 21.Power-On Reset and Power-Up Clear Schematic 2.1.1 Brownout Reset (BOR) Figure 22. Brownout Timing 2.1.2 Device Initial Conditions After System Reset Software Initialization 2.2 Interrupts Figure 23. Interrupt Priority 2.2.1 (Non)-Maskable Interrupts (NMI) Reset/NMI Pin System Reset and Initialization 2-7System Resets, Interrupts, and Operating Modes Figure 24. Block Diagram of (Non)-Maskable Interrupt Sources Oscillator Fault Flash Access Violation Example of an NMI Interrupt Handler Figure 25. NMI Interrupt Handler 2.2.2 Maskable Interrupts 2.2.3 Interrupt Processing Interrupt Acceptance Figure 26. Interrupt Processing Return From Interrupt Figure 27. Return From Interrupt 2.2.4 Interrupt Vectors Table 21.Interrupt Sources,Flags, and Vectors 2.2.5 Special Function Registers (SFRs) 2.3 Operating Modes Figure 28. Typical Current Consumption of 41x Devices vs Operating Modes Figure 29. MSP430x4xx Operating Modes For Basic Clock System 2.3.1 Entering and Exiting Low-Power Modes Extended Time in Low-Power Modes 2.4 Principles for Low-Power Applications 2.5 Connection of Unused Pins Table 22.Connection of Unused Pins 3.1 CPU Introduction CPU Introduction 3-3RISC 16-Bit CPU Figure 31.CPU Block Diagram 3.2 CPU Registers 3.2.1 Program Counter (PC) Figure 32. Program Counter 3.2.2 Stack Pointer (SP) Figure 33. Stack Pointer Figure 34. Stack Usage Figure 35. PUSH SP - POP SP Sequence 3.2.3 Status Register (SR) Figure 36. Status Register Bits Table 31 describes the status register bits. Table 31.Description of Status Register Bits 3.2.4 Constant Generator Registers CG1 and CG2 Table 32.Values of Constant Generators CG1, CG2 Constant Generator Expanded Instruction Set 3.2.5 GeneralPurpose Registers R4 - R15 Figure 3 7. Register 3.3 Addressing Modes Table 33.Source/Destination Operand Addressing Modes 3.3.1 Register Mode Table 34.Register Mode Description 3.3.2 Indexed Mode The indexed mode is described in Table 35. Table 35.Indexed Mode Description 3.3.3 Symbolic Mode Table 36.Symbolic Mode Description 3.3.4 Absolute Mode Table 37.Absolute Mode Description 3.3.5 Indirect Register Mode The indirect register mode is described in Table 38. Table 38.Indirect Mode Description 3.3.6 Indirect Autoincrement Mode The indirect autoincrement mode is described in Table 39. Table 39.Indirect Autoincrement Mode Description Figure 38. Operand Fetch Operation 3.3.7 Immediate Mode Table 310.Immediate Mode Description 3.4 Instruction Set 3.4.1 Double-Operand (Format I) Instructions Figure 39. Double Operand Instruction Format Table 311.Double Operand Instructions 3.4.2 Single-Operand (Format II) Instructions Figure 310. Single Operand Instruction Format Table 312.Single Operand Instructions 3.4.3 Jumps Figure 311. Jump Instruction Format Table 313.Jump Instructions Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Figure 312. Decrement Overlap Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Figure 313. Main Program Interrupt Figure 314. Destination OperandArithmetic Shift Left Figure 315. Destination OperandCarry Left Shift Figure 316. Destination OperandArithmetic Right Shift Figure 317. Destination OperandCarry Right Shift Page Page Page Page Page Page Figure 318. Destination Operand Byte Swap Figure 319. Destination Operand Sign Extension Page Page 3.4.4 Instruction Cycles and Lengths Interrupt and Reset Cycles Table 314.Interrupt and Reset Cycles Format-II (Single Operand) Instruction Cycles and Lengths Table 315.Format-II Instruction Cycles and Lengths Format-I (Double Operand) Instruction Cycles and Lengths Table 316 lists the length and CPU cycles for all addressing modes of format-I instructions. Table 316.Format I Instruction Cycles and Lengths Instruction Set 3-74 RISC 16Bit CPU 3.4.5 Instruction Set Description Figure 320. Core Instruction Map Instruction Set RISC 16Bit CPU 3-75 Table 317.MSP430 Instruction Set 4.1 FLL+ Clock Module Introduction 4-3FLL+ Clock Module Figure 41.MSP430x44x and MSP430x43x Frequency-Locked Loop 4-4 FLL+ Clock Module Figure 42. MSP430x42x and MSP430x41x Frequency-Locked Loop 4.2 FLL+ Clock Module Operation 4.2.1 FLL+ Clock features for Low-Power Applications 4.2.2 LFXT1 Oscillator 4.2.3 XT2 Oscillator 4.2.4 Digitally-Controlled Oscillator (DCO) DCO Frequency Range Table 41.DCO Range Control Bits 4.2.5 Frequency Locked Loop (FLL) 4.2.6 DCO Modulator Figure 43. Modulator Patterns 4.2.7 Disabling the FLL Hardware and Modulator 4.2.8 FLL Operation from Low-Power Modes- 4.2.9 Buffered Clock Output 4.2.10 FLL+ Fail-Safe Operation Figure 44. Oscillator Fault Logic 4.3 FLL+ Clock Module Registers Table 42.FLL+ Registers SCFQCTL, System Clock Control Register SCFI0, System Clock Frequency Integrator Register 0 SCFI1, System Clock Frequency Integrator Register 1 FLL_CTL0, FLL+ Control Register 0 FLL_CTL1, FLL+ Control Register 1 Page 5.1 Flash Memory Introduction Figure 51.Flash Memory Module Block Diagram 5.2 Flash Memory Segmentation Figure 5 2. 5.3 Flash Memory Operation 5.3.1 Flash Memory Timing Generator Figure 53. Flash Memory Timing Generator Block Diagram 5.3.2 Erasing Flash Memory Table 51.Erase Modes Figure 54. Erase Cycle Timing Initiating an Erase from Within Flash Memory Figure 55. Erase Cycle from Within Flash Memory Initiating an Erase from RAM Figure 56. Erase Cycle from Within RAM 5.3.3 Writing Flash Memory Table 52.Write Modes Byte/Word Write Figure 57. Byte/Word Write Timing Initiating a Byte/Word Write from Within Flash Memory Figure 58. Initiating a Byte/Word Write from Flash Initiating a Byte/Word Write from RAM The flow to initiate a byte/word write from RAM is shown in Figure 59. Figure 59. Initiating a Byte/Word Write from RAM Block Write Figure 510. Block-Write Cycle Timing Block Write Flow and Example A block write flow is shown in Figure 58 and the following example. Figure 511. Block Write Flow Page 5.3.4 Flash Memory Access During Write or Erase Table 53.Flash Access While BUSY = 1 5.3.5 Stopping a Write or Erase Cycle 5.3.6 Configuring and Accessing the Flash Memory Controller 5.3.7 Flash Memory Controller Interrupts 5.3.8 Programming Flash Memory Devices Programming Flash Memory via JTAG Programming Flash Memory via the Bootstrap loader (BSL) Programming Flash Memory via a Custom Solution Figure 512. User-Developed Programming Solution 5.4 Flash Memory Registers The flash memory registers are listed in Table 54. Table 54.Flash Memory Registers FCTL1, Flash Memory Control Register FCTL2, Flash Memory Control Register FCTL3, Flash Memory Control Register FCTL3 Page 6.1 SVS Introduction SVS Introduction 6-3Supply Voltage Supervisor Figure 61.SVS Block Diagram 6.2 SVS Operation 6.2.1 Configuring the SVS 6.2.2 SVS Comparator Operation 6.2.3 Changing the VLDx Bits Figure 62. SVSON state When Changing VLDx SVS Operation 6-6 Supply Voltage Supervisor 6.2.4 SVS Operating Range Figure 63. Operating Levels for SVS and Brownout/Reset Circuit 6.3 SVS Registers Table 61.SVS Registers SVSCTL, SVS Control Register Hardware Multiplier 7.1 Hardware Multiplier Introduction Figure 71.Hardware Multiplier Block Diagram 7.2 Hardware Multiplier Operation 7.2.1 Operand Registers Table 71.OP1 addresses 7.2.2 Result Registers Table 72.RESHI Contents Table 73.SUMEXT Contents MACS Underflow and Overflow 7.2.3 Software Examples 7.2.4 Indirect Addressing of RESLO 7.2.5 Using Interrupts 7.3 Hardware Multiplier Registers The hardware multiplier registers are listed in Table 74. Table 74.Hardware Multiplier Registers 8.1 DMA Introduction 8-3 Figure 81.DMA Controller Block Diagram 8.2 DMA Operation 8.2.1 DMA Addressing Modes Figure 82. DMA Addressing Modes 8.2.2 DMA Transfer Modes Table 81.DMA Transfer Modes Single Transfer 8-7 Figure 83. DMA Single Transfer State Diagram Block Transfers 8-9 Figure 84. DMA Block Transfer State Diagram Burst-Block Transfers 8-11 Figure 85. DMA Burst-Block Transfer State Diagram 8.2.3 Initiating DMA Transfers Edge-Sensitive Triggers Level-Sensitive Triggers Halting Executing Instructions for DMA Transfers Table 82.DMA Trigger Operation 8.2.4 Stopping DMA Transfers 8.2.5 DMA Channel Priorities 8.2.6 DMA Transfer Cycle Time Table 83.Maximum Single-Transfer DMA Cycle Time 8.2.7 Using DMA with System Interrupts 8.2.8 DMA Controller Interrupts 8.2.9 Using the I2C Module with the DMA Controller 8.2.10 Using ADC12 with the DMA Controller 8.2.11 Using DAC12 With the DMA Controller 8.3 DMA Registers The DMA registers are listed in Table 84. Table 84.DMA Registers DMACTL0, DMA Control Register 0 DMACTL1, DMA Control Register 1 DMAxCTL, DMA Channel x Control Register DMAxSA, DMA Source Address Register DMAxDA, DMA Destination Address Register DMAxSZ, DMA Size Address Register Digital I/O 9.1 Digital I/O Introduction 9.2 Digital I/O Operation 9.2.1 Input Register PxIN 9.2.2 Output Registers PxOUT 9.2.3 Direction Registers PxDIR 9.2.4 Function Select Registers PxSEL 9.2.5 P1 and P2 Interrupts Interrupt Flag Registers P1IFG, P2IFG Interrupt Edge Select Registers P1IES, P2IES Interrupt Enable P1IE, P2IE 9.2.6 Configuring Unused Port Pins 9.3 Digital I/O Registers Table 91.Digital I/O Registers 10.1 Watchdog Timer Introduction Watchdog Timer Introduction 10-3Watchdog Timer, Watchdog Timer+ Figure 101. Watchdog Timer Block Diagram 10.2 Watchdog Timer Operation 10.2.1 Watchdog Timer Counter 10.2.2 Watchdog Mode 10.2.3 Interval Timer Mode 10.2.4 Watchdog Timer Interrupts 10.2.5 WDT+ Enhancements 10.2.6 Operation in Low-Power Modes 10.2.7 Software Examples 10.3 Watchdog Timer Registers The watchdog timer module registers are listed in Table 101. Table 101.Watchdog Timer Registers WDTCTL, Watchdog Timer Register Page Page 11.1 Basic Timer1 Introduction Basic Timer1 Introduction 11-3Basic Timer1 Figure 111. Basic Timer1 Block Diagram 11.2 Basic Timer1 Operation 11.2.1 Basic Timer1 Counter One 11.2.2 Basic Timer1 Counter Two 11.2.3 16-bit Counter Mode 11.2.4 Basic Timer1 Operation: Signal f 11.2.5 Basic Timer1 Interrupts 11.3 Basic Timer1 Registers The watchdog timer module registers are listed in Table 111. Table 111.Basic Timer1 Registers BTCTL, Basic Timer1 Control Register BTCNT1, Basic Timer1 Counter 1 BTCNT2, Basic Timer1 Counter 2 Page Timer_A 12.1 Timer_A Introduction Timer_A Introduction 12-3Timer_A Figure 121. Timer_A Block Diagram 12.2 Timer_A Operation 12.2.1 16-Bit Timer Counter Clock Source Select and Divider 12.2.2 Starting the Timer 12.2.3 Timer Mode Control Table 121.Timer Modes Up Mode Figure 122. Up Mode Figure 123. Up Mode Flag Setting Page Use of the Continuous Mode Figure 126. Continuous Mode Time Intervals Up/Down Mode Figure 127. Up/Down Mode Figure 128. Up/Down Mode Flag Setting Use of the Up/Down Mode Figure 129. Output Unit in Up/Down Mode 12.2.4 Capture/Compare Blocks Capture Mode Figure 1210. Capture Signal (SCS=1) Figure 1211.Capture Cycle Compare Mode 12.2.5 Output Unit Output Modes Table 122.Output Modes Figure 1212. Output ExampleTimer in Up Mode Figure 1213. Output ExampleTimer in Continuous Mode Figure 1214. Output ExampleTimer in Up/Down Mode 12.2.6 Timer_A Interrupts TACCR0 Interrupt Figure 1215. Capture/Compare TACCR0 Interrupt Flag TAIV, Interrupt Vector Generator Page 12.3 Timer_A Registers The Timer_A registers are listed in Table 123 and Table 124. Table 123.Timer_A3 Registers Table 124.Timer1_A5 Registers TACTL, Timer_A Control Register TAR, Timer_A Register TACCTLx, Capture/Compare Control Register TAIV, Timer_A Interrupt Vector Register Timer_B 13.1 Timer_B Introduction 13.1.1 Similarities and Differences From Timer_A Timer_B Introduction 13-3Timer_B Figure 131. Timer_B Block Diagram 13.2 Timer_B Operation 13.2.1 16-Bit Timer Counter TBR Length Clock Source Select and Divider 13.2.2 Starting the Timer 13.2.3 Timer Mode Control Table 131.Timer Modes Up Mode Figure 132. Up Mode Figure 133. Up Mode Flag Setting Continuous Mode Figure 134. Continuous Mode Figure 135. Continuous Mode Flag Setting Use of the Continuous Mode Figure 136. Continuous Mode Time Intervals Up/Down Mode Figure 137. Up/Down Mode Figure 138. Up/Down Mode Flag Setting Use of the Up/Down Mode Figure 139. Output Unit in Up/Down Mode 13.2.4 Capture/Compare Blocks Capture Mode Figure 1310. Capture Signal (SCS=1) Figure 1311.Capture Cycle Compare Mode Table 132.TBCLx Load Events Table 133.Compare Latch Operating Modes 13.2.5 Output Unit Output Modes Table 134.Output Modes Figure 1312. Output ExampleTimer in Up Mode Figure 1313. Output ExampleTimer in Continuous Mode Figure 1314. Output ExampleTimer in Up/Down Mode 13.2.6 Timer_B Interrupts Figure 1315. Capture/Compare TBCCR0 Interrupt Flag TBIV, Interrupt Vector Generator TBIV, Interrupt Handler Examples 13.3 Timer_B Registers The Timer_B registers are listed in Table 135. Table 135.Timer_B Registers Timer_B Control Register TBCTL TBR, Timer_B Register TBCCTLx, Capture/Compare Control Register Page TBIV, Timer_B Interrupt Vector Register 15-0 Timer_B interrupt vector value 14.1 USART Introduction: UART Mode USART Introduction: UART Mode 14-3USART Peripheral Interface, UART Mode Figure 141. USART Block Diagram: UART Mode 14.2 USART Operation: UART Mode 14.2.1 USART Initialization and Reset 14.2.2 Character Format Figure 142. Character Format 14.2.3 Asynchronous Communication Formats Idle-Line Multiprocessor Format Figure 143. Idle-Line Format Page Address-Bit Multiprocessor Format Figure 144. Address-Bit Multiprocessor Format Automatic Error Detection Table 141.Receive Error Conditions 14.2.4 USART Receive Enable Figure 145. State Diagram of Receiver Enable 14.2.5 USART Transmit Enable Figure 146. State Diagram of Transmitter Enable USART Operation: UART Mode 14-11USART Peripheral Interface, UART Mode 14.2.6 UART Baud Rate Generation Figure 147. MSP430 Baud Rate Generator Figure 148. BITCLK Baud Rate Timing Baud Rate Bit Timing Determining the Modulation Value Page Receive Bit Timing Figure 149. Receive Error Page USART Operation: UART Mode 14-16 USART Peripheral Interface, UART Mode Typical Baud Rates and Errors Table 142.Commonly Used Baud Rates, Baud Rate Data, and Errors 14.2.7 USART Interrupts USART Transmit Interrupt Operation Figure 1410. Transmit Interrupt Operation USART Receive Interrupt Operation Figure 1411.Receive Interrupt Operation Receive-Start Edge Detect Operation Figure 1412. Glitch Suppression, USART Receive Not Started Figure 1413. Glitch Suppression, USART Activated 14.3 USART Registers: UART Mode Table 143.USART0 Control and Status Registers Table 144.USART1 Control and Status Registers UxCTL, USART Control Register UxTCTL, USART Transmit Control Register UxRCTL, USART Receive Control Register USART Registers: UART Mode 14-25USART Peripheral Interface, UART Mode UxBR0, USART Baud Rate Control Register 0 UxBR1, USART Baud Rate Control Register 1 70Modulation bits. These bits select the modulation for BRCLK. UxBRx The valid baud-rate control range is 3 UxBR < 0FFFFh, where UxBR = {UxBR1+UxBR0}. Unpredictable receive and transmit timing occurs if UxBR <3. UxRXBUF, USART Receive Buffer Register UxTXBUF, USART Transmit Buffer Register ME1, Module Enable Register 1 ME2, Module Enable Register 2 Page Page USART Peripheral Interface, SPI Mode 15.1 USART Introduction: SPI Mode USART Introduction: SPI Mode 15-3USART Peripheral Interface, SPI Mode Figure 151. USART Block Diagram: SPI Mode 15.2 USART Operation: SPI Mode 15.2.1 USART Initialization and Reset 15.2.2 Master Mode Figure 152. USART Master and External Slave Four-Pin SPI Master Mode 15.2.3 Slave Mode Figure 153. USART Slave and External Master Four-Pin SPI Slave Mode 15-7USART Peripheral Interface, SPI Mode 15.2.4 SPI Enable Transmit Enable Figure 154. Master Mode Transmit Enable Figure 155. Slave Transmit Enable State Diagram 15-8 USART Peripheral Interface, SPI Mode Receive Enable Figure 156. SPI Master Receive-Enable State Diagram Figure 157. SPI Slave Receive-Enable State Diagram 15.2.5 Serial Clock Control Figure 158. SPI Baud Rate Generator 15-10 USART Peripheral Interface, SPI Mode Serial Clock Polarity and Phase Figure 159. USART SPI Timing 15.2.6 SPI Interrupts SPI Transmit Interrupt Operation Figure 1510. Transmit Interrupt Operation 15-12 USART Peripheral Interface, SPI Mode SPI Receive Interrupt Operation Figure 1511.Receive Interrupt Operation Figure 1512. Receive Interrupt State Diagram 15.3 USART Registers: SPI Mode Table 151.USART0 Control and Status Registers Table 152.USART1 Control and Status Registers UxCTL, USART Control Register UxTCTL, USART Transmit Control Register UxRCTL, USART Receive Control Register USART Registers: SPI Mode 15-17USART Peripheral Interface, SPI Mode UxBR0, USART Baud Rate Control Register 0 UxBR1, USART Baud Rate Control Register 1 to 000h. 70The modulation control register is not used for SPI mode and should be set UxBRx The baud-rate generator uses the content of {UxBR1+UxBR0} to set the UxRXBUF, USART Receive Buffer Register UxTXBUF, USART Transmit Buffer Register ME1, Module Enable Register 1 ME2, Module Enable Register 2 Page Page OA 16.1 OA Introduction OA Introduction 16-3OA Figure 161. OA Block Diagram 16.2 OA Operation 16.2.1 OA Amplifier 16.2.2 OA Input 16.2.3 OA Output 16.2.4 OA Configurations Table 161.OA Mode Select General Purpose Opamp Mode Unity Gain Mode Comparator Mode Non-Inverting PGA Mode Inverting PGA Mode Differential Amplifier Mode Table 162.Two-Opamp Differential Amplifier Control Register Settings Table 163.Two-Opamp Differential Amplifier Gain Settings Figure 162. Two Opamp Differential Amplifier OA 16-8 OA Figure 163. Two Opamp Differential Amplifier OAx Interconnections Table 164.Three-Opamp Differential Amplifier Control Register Settings Table 165.Three-Opamp Differential Amplifier Gain Settings Figure 164. Three Opamp Differential Amplifier OA 16-10 OA Figure 165. Three Opamp Differential Amplifier OAx Interconnections 16.3 OA Registers The OA registers are listed in Table 166. Table 166. OAxCTL0, Opamp Control Register 0 OAxCTL1, Opamp Control Register 1 Comparator_A 17.1 Comparator_A Introduction Comparator_A Introduction 17-3Comparator_A Figure 171. Comparator_A Block Diagram 17.2 Comparator_A Operation 17.2.1 Comparator 17.2.2 Input Analog Switches 17.2.3 Output Filter Figure 172. RC-Filter Response at the Output of the Comparator 17.2.4 Voltage Reference Generator 17.2.5 Comparator_A, Port Disable Register CAPD Figure 173. Transfer Characteristic and Power Dissipation in a CMOS Inverter/Buffer 17.2.6 Comparator_A Interrupts Figure 174. Comparator_A Interrupt System 17.2.7 Comparator_A Used to Measure Resistive Elements Figure 175. Temperature Measurement System Figure 176. Timing for Temperature Measurement Systems Page CACTL1, Comparator_A Control Register 1 CACTL2, Comparator_A Control Register 2 CAPD, Comparator_A Port Disable Register LCD Controller 18.1 LCD Controller Introduction LCD Controller Introduction 18-3LCD Controller Figure 181. LCD Controller Block Diagram 18.2 LCD Controller Operation 18.2.1 LCD Memory Figure 182. LCD memory 18.2.2 Blinking the LCD 18.2.3 LCD Timing Generation 18.2.4 LCD Voltage Generation Table 181.External LCD Module Analog Voltage LCD Contrast Control 18.2.5 LCD Outputs 18.2.6 Static Mode Figure 183. Example Static Waveforms Figure 184 shows an example static LCD, pin-out, LCD-to-MSP430 Figure 184. Static LCD Example Static Mode Software Example 18.2.7 2-Mux Mode Figure 185. Example 2-Mux Waveforms Figure 186 shows an example 2-mux LCD, pin-out, LCD-to-MSP430 Figure 186. 2Mux LCD Example 2-Mux Mode Software Example 18-12 LCD Controller 18.2.8 3-Mux Mode Figure 187. Example 3-Mux Waveforms Segment e (COM0SP1) Segment d (COM0SP2) 18-13LCD Controller Figure 188. 3-Mux LCD Example y y DIGIT10 DIGIT1 3-Mux Mode Software Example 18-15LCD Controller 18.2.9 4-Mux Mode Figure 189. Example 4-Mux Waveforms Segment e (COM1SP1) Segment c (COM1SP2) 18-16 LCD Controller Figure 1810. 4-Mux LCD Example DIGIT15 DIGIT1 4-Mux Mode Software Example 18.3 LCD Controller Registers The LCD Controller registers are listed in Table 182. Table 182.LCD Controller Registers LCDCTL, LCD Control Register LCD_A Controller 19.1 LCD_A Controller Introduction LCD_A Controller Introduction 19-3LCD_A Controller Figure 191. LCD_A Controller Block Diagram 19.2 LCD_A Controller Operation 19.2.1 LCD Memory Figure 192. LCD memory 19.2.2 Blinking the LCD 19.2.3 LCD_A Voltage And Bias Generation LCD Voltage Selection LCD Bias Generation 19-6 LCD_A Controller Figure 193. Bias Generation LCD Contrast Control Table 191.LCD Voltage and Biasing Characteristics 19.2.4 LCD Timing Generation 19.2.5 LCD Outputs 19.2.6 Static Mode Figure 194. Example Static Waveforms Figure 195 shows an example static LCD, pin-out, LCD-to-MSP430 Figure 195. Static LCD Example Static Mode Software Example 19.2.7 2-Mux Mode Figure 196. Example 2-Mux Waveforms Figure 197 shows an example 2-mux LCD, pin-out, LCD-to-MSP430 Figure 197. 2Mux LCD Example 2-Mux Mode Software Example 19-15LCD_A Controller 19.2.8 3-Mux Mode Figure 198. Example 3-Mux Waveforms Segment e (COM0SP1) Segment d (COM0SP2) 19-16 LCD_A Controller Figure 199. 3-Mux LCD Example y y DIGIT10 DIGIT1 3-Mux Mode Software Example 19-18 LCD_A Controller 19.2.9 4-Mux Mode Figure 1910. Example 4-Mux Waveforms Segment e (COM1SP1) Segment c (COM1SP2) 19-19LCD_A Controller Figure 1911.4-Mux LCD Example DIGIT15 DIGIT1 4-Mux Mode Software Example 19.3 LCD Controller Registers The LCD Controller registers are listed in Table 192. Table 192.LCD Controller Registers LCDACTL, LCD_A Control Register LCDAPCTL0, LCD_A Port Control Register 0 LCDAPCTL1, LCD_A Port Control Register 1 LCDAVCTL0, LCD_A Voltage Control Register 0 LCDAVCTL1, LCD_A Voltage Control Register 1 ADC12 20.1 ADC12 Introduction ADC12 Introduction 20-3ADC12 Figure 201. ADC12 Block Diagram 20.2 ADC12 Operation 20.2.1 12-Bit ADC Core Conversion Clock Selection 20.2.2 ADC12 Inputs and Multiplexer Figure 202. Analog Multiplexer Analog Port Selection 20.2.3 Voltage Reference Generator 20.2.4 Auto Power-Down 20.2.5 Sample and Conversion Timing Extended Sample Mode Figure 203. Extended Sample Mode Pulse Sample Mode Figure 204. Pulse Sample Mode Sample Timing Considerations Figure 205. Analog Input Equivalent Circuit 20.2.6 Conversion Memory 20.2.7 ADC12 Conversion Modes Table 201.Conversion Mode Summary Single-Channel Single-Conversion Mode Figure 206. Single-Channel, Single-Conversion Mode Sequence-of-Channels Mode Figure 207. Sequence-of-Channels Mode Repeat-Single-Channel Mode Figure 208. Repeat-Single-Channel Mode Repeat-Sequence-of-Channels Mode Figure 209. Repeat-Sequence-of-Channels Mode Using the Multiple Sample and Convert (MSC) Bit Stopping Conversions 20.2.8 Using the Integrated Temperature Sensor Figure 2010. Typical Temperature Sensor Transfer Function 20.2.9 ADC12 Grounding and Noise Considerations Figure 2011.ADC12 Grounding and Noise Considerations 20.2.10 ADC12 Interrupts ADC12IV, Interrupt Vector Generator ADC12 Interrupt Handling Software Example 20.3 ADC12 Registers The ADC12 registers are listed in Table 202 . Table 202.ADC12 Registers ADC12CTL0, ADC12 Control Register 0 15-12 Sample-and-hold time. These bits define the number of ADC12CLK cycles in 11-8 Sample-and-hold time. These bits define the number of ADC12CLK cycles in the sampling period for registers ADC12MEM8 to ADC12MEM15. the sampling period for registers ADC12MEM0 to ADC12MEM7. Page ADC12CTL1, ADC12 Control Register 1 ADC12MEMx, ADC12 Conversion Memory Registers ADC12MCTLx, ADC12 Conversion Memory Control Registers ADC12IE, ADC12 Interrupt Enable Register ADC12IFG, ADC12 Interrupt Flag Register ADC12IV, ADC12 Interrupt Vector Register 15-0 ADC12 interrupt vector value SD16 21.1 SD16 Introduction SD16 Introduction 21-3SD16 Figure 211. SD16 Block Diagram 21.2 SD16 Operation 21.2.1 ADC Core 21.2.2 Analog Input Range and PGA 21.2.3 Voltage Reference Generator 21.2.4 Auto Power-Down 21.2.5 Channel Selection Analog Input Setup Analog Input Characteristics Anti-Aliasing Filter Page Figure 213. Digital Filter Step Response and Conversion Points Digital Filter Output Figure 214. Used Bits of Digital Filter Output. 21.2.7 Conversion Memory Registers: SD16MEMx Output Data Format Table 211.Data Format Figure 215. Input Voltage vs. Digital Output 21.2.8 Conversion Modes Table 212.Conversion Mode Summary Single Channel, Single Conversion Single Channel, Continuous Conversion Figure 216. Single Channel Operation Group of Channels, Single Conversion Group of Channels, Continuous Conversion Figure 217. Grouped Channel Operation 21.2.9 Conversion Operation Using Preload Figure 218. Conversion Delay using Preload SD16 Operation 21-14 SD16 Figure 219. Start of Conversion using Preload Figure 2110. Preload and Channel Synchronization 21.2.10 Using the Integrated Temperature Sensor Figure 2111.Typical Temperature Sensor Transfer Function 21.2.11 Interrupt Handling SD16IV, Interrupt Vector Generator Interrupt Delay Operation SD16 Interrupt Handling Software Example 21.3 SD16 Registers The SD16 registers are listed in Table 213: Table 213.SD16 Registers SD16CTL, SD16 Control Register SD16CCTLx, SD16 Channel x Control Register SD16INCTLx, SD16 Channel x Input Control Register SD16MEMx, SD16 Channel x Conversion Memory Register SD16PREx, SD16 Channel x Preload Register SD16IV, SD16 Interrupt Vector Register 15-0 SD16 interrupt vector value SD16_A 22.1 SD16_A Introduction SD16_A Introduction 22-3SD16_A Figure 221. SD16_A Block Diagram 22.2 SD16_A Operation 22.2.1 ADC Core 22.2.2 Analog Input Range and PGA 22.2.3 Voltage Reference Generator 22.2.4 Auto Power-Down 22.2.5 Channel Selection Analog Input Setup Table 221.High Input Impedance Buffer 22.2.6 Analog Input Characteristics Page Figure 223. Digital Filter Step Response and Conversion Points Digital Filter Output Figure 224. Used Bits of Digital Filter Output SD16_A Operation 22-9SD16_A 22.2.8 Conversion Memory Register: SD16MEM0 Output Data Format Table 222.Data Format Figure 225. Input Voltage vs. Digital Output 22.2.9 Conversion Modes Table 223.Conversion Mode Summary Single Conversion Continuous Conversion Figure 226. Single Channel Operation 22.2.10 Using the Integrated Temperature Sensor Figure 227. Typical Temperature Sensor Transfer Function 22.2.11 Interrupt Handling SD16IV, Interrupt Vector Generator Interrupt Delay Operation 22.3 SD16_A Registers The SD16_A registers are listed in Table 224: Table 224.SD16_A Registers SD16CTL, SD16_A Control Register SD16CCTL0, SD16_A Control Register 0 Page SD16INCTL0, SD16_A Input Control Register SD16MEM0, SD16_A Conversion Memory Register SD16AE, SD16_A Analog Input Enable Register SD16IV, SD16_A Interrupt Vector Register 15-0 SD16_A interrupt vector value DAC12 23.1 DAC12 Introduction DAC12 Introduction 23-3DAC12 Figure 231. DAC12 Block Diagram DAC12 Introduction 23-4 DAC12 Figure 232. DAC12 Block Diagram For MSPx42x0 Devices 23.2 DAC12 Operation 23.2.1 DAC12 Core Table 231.DAC12 Full-Scale Range (Vref = VeREF+ or VREF+) DAC12 Port Selection 23.2.2 DAC12 Reference DAC12 Reference Input and Voltage Output Buffers 23.2.3 Updating the DAC12 Voltage Output 23.2.4 DAC12_xDAT Data Format Figure 233. Output Voltage vs DAC12 Data, 12-Bit, Straight Binary Mode Figure 234. Output Voltage vs DAC12 Data, 12-Bit, 2s Compliment Mode 23.2.5 DAC12 Output Amplifier Offset Calibration Figure 235. Negative Offset Figure 236. Positive Offset 23.2.6 Grouping Multiple DAC12 Modules Figure 237. DAC12 Group Update Example, Timer_A3 Trigger 23.2.7 DAC12 Interrupts 23.3 DAC12 Registers The DAC12 registers are listed in Table 232. Table 232.DAC12 Registers DAC12_xCTL, DAC12 Control Register Page DAC12_xDAT, DAC12 Data Register 15-12 Unused. These bits are always 0 and do not affect the DAC12 core. 11-0 DAC12 data 24.1 Scan IF Introduction Scan IF Introduction 24-3Scan IF Figure 241. Scan IF Block Diagram 24.2 Scan IF Operation 24.2.1 Scan IF Analog Front End 24-5Scan IF Figure 242. Scan IF Analog Front End Block Diagram Excitation Mid-Voltage Generator 24-7Scan IF Figure 243. Excitation and Sample-And-Hold Circuitry Sample-And-Hold Figure 244. Analog Input Equivalent Circuit Direct Analog And Digital Inputs Comparator Input Selection And Output Bit Selection Table 241.SIFCAX and SIFSH Input Selection Table 242.Selected Output Bits Figure 245. Analog Front-End Output Timing Comparator and DAC Table 243.Selected DAC Registers Figure 246. Analog Hysteresis With DAC Registers Table 244.DAC Register Select When TESTDX = 1 Internal Signal Connections to Timer1_A5 Figure 247. TimerA Output Stage of the Analog Front End 24.2.2 Scan IF Timing State Machine 24-15Scan IF Figure 248. Timing State Machine Block Diagram TSM Operation TSM Control of the AFE TSM State Duration Table 245.TSM State Duration TSM State Clock Source Select TSM Stop Condition TSM Test Cycles Figure 249. Test Cycle Insertion TSM Example Table 246.TSM Example Register Values Figure 2410. Timing State Machine Example 24.2.3 Scan IF Processing State Machine 24-21Scan IF Figure 2411.Scan IF Processing State Machine Block Diagram PSM Operation Next State Calculation PSM Counters Simplest State Machine Figure 2412. Simplest PSM State Diagram Page 24.2.4 Scan IF Debug Register 24.2.5 Scan IF Interrupts Table 247.Scan IF Interrupts Figure 2413. Interrupt Hysteresis Shown For Modulo 4 Interrupt Generation 24.2.6 Using the Scan IF with LC Sensors Figure 2414. LC Sensor Oscillations Figure 2415. LC Sensor Connections For The Oscillation Test Figure 2416. LC Sensor Connections For The Envelope Test 24-31Scan IF Figure 2417. LC Sensor Connections For The Envelope Test 24.2.7 Using the Scan IF With Resistive Sensors Figure 2418. Resistive Sensor Connections 24.2.8 Quadrature Decoding Figure 2419. Sensor Position and Quadrature Signals Figure 2420. Quadrature Decoding State Diagram Table 248.Quadrature Decoding PSM Table 24.3 Scan IF Registers The Scan IF registers are listed in Table 249. Table 249.Scan IF Registers SIFDEBUG, Scan IF Debug Register, Write Mode SIFDEBUG, Scan IF Debug Register, Read Mode After 00h Is Written SIFDEBUG, Scan IF Debug Register, Read Mode After 01h Is Written SIFDEBUG, Scan IF Debug Register, Read Mode After 02h Is Written SIFDEBUG, Scan IF Debug Register, Read Mode After 03h Is Written SIFCNT, Scan IF Counter Register SIFPSMV, Scan IF Processing State Machine Vector Register SIFCTL1, Scan IF Control Register 1 Page SIFCTL2, Scan IF Control Register 2 Page SIFCTL3, Scan IF Control Register 3 Page SIFCTL4, Scan IF Control Register 4 Page SIFCTL5, Scan IF Control Register 5 SIFDACRx, Digital-To-Analog Converter Registers SIFTSMx, Scan IF Timing State Machine Registers Page Processing State Machine Table Entry (MSP430 Memory Location)