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Texas Instruments TMS320C6457 manual HPI Signals, continued, Introduction to the HPI, Hr/W

Models: TMS320C6457

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Introduction to the HPI

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Signal

State (1)

HCNTL[1:0] I

HR/WI

HHWILI

HASI

	HD[31:0]			I/O/Z
	HD[15:0]

				O/Z
	HRDY

				O/Z
	HINT

Table 2. HPI Signals

(continued)

Host Connection

Description

Address or control pins

The HPI latches the logic levels of these pins on the

falling edge of

HAS

or internal

HSTRB

(for details

about internal

HSTRB,

see Section 3.3). The four

binary states of these pins determine the access type

of the current transfer (HPIC, HPID with

autoincrementing, HPIA, or HPID without

autoincrementing).

R/W strobe pin

HPI read/write. On the falling edge of

or internal

HAS

indicates whether the current access is

HSTRB,

HR/W

high

to be a read or write operation. Driving HR/W

indicates the transfer is a read from the HPI, while

low indicates a write to the HPI.

driving HR/W

Address or control pins

Halfword identification control input. This bit identifies

the first and second halfwords of a dual halfword cycle

operation. HHWIL=0 identifies the first cycle and

HHWIL=1 identifies the second cycle. HHWIL applies

only to HPI16 mode and not to HPI32 mode.

ALE (address latch enable) or

Address strobe. A host with a multiplexed address/data

address strobe pin

bus can have

HAS

connected to its ALE pin. The

falling edge of

HAS

latches the logic levels of the

HCNTL1, and HCNTL0 pins, which are typically

HR/W,

connected to host address lines. When used, the

HAS

signal must precede the falling edge of the internal

HSTRB

signal.

Data bus

The HPI data bus carries the data to/from the HPI.

HD[31:0] applies to HPI32 and HD[15:0] applies to

HPI16.

Asynchronous ready pin

When the HPI drives

low, the host has

HRDY

permission to complete the current host cycle. When

the HPI drives

HRDY

high, the HPI is not ready for the

current host cycle to complete.

Interrupt pin

The DSP can interrupt the host processor by writing a

1 to the HINT bit of HPIC. Before subsequent HINT

interrupts can occur, the host must clear previous

interrupts by writing a 1 to the HINT bit. This pin is

active-low and inverted from the HINT bit value in

HPIC.

10

Host Port Interface (HPI)

SPRUGK7A –March 2009 –Revised July 2010

Copyright © 2009–2010, Texas Instruments Incorporated

Image 10

Texas Instruments TMS320C6457 manual HPI Signals, continued, Introduction to the HPI, Host Port Interface HPI, Hr/W

Contents

Users Guide TMS320C6457 DSP Host Port Interface HPISPRUGK7A -March 2009 -Revised July Copyright 2009-2010, Texas Instruments IncorporatedIntroduction to the HPI List of Figures List of FiguresList of Tables About This Manual Read This FirstPreface Notational Conventions1 Introduction to the HPI Host Port Interface HPIUsers Guide Figure 1. HPI Position in the Host-DSP System1.1 Summary of the HPI Registers Introduction to the HPITable 2. HPI Signals 1.2 Summary of the HPI SignalsTable 1. Summary of HPI Registers Introduction to the HPI Table 2. HPI Signalscontinued Host Port Interface HPI2.1 Single-HPIA Mode 2 Using the Address Registers2.2 Dual-HPIA Mode in the 32-Bit Multiplexed Mode 3.1 Host-HPI Signal Connections3 HPI Operation in the 32-Bit Multiplexed Mode in the 16-Bit Multiplexed Mode3.2 HPI Configuration and Data Flow Multiplexed Mode3.3 HDS2, HDS1, and HCS Data Strobing and Chip Selection Table 3. Options for Connecting Host and HPI Data Strobe PinsFigure 6. HPI Strobe and Select Logic Table 5. Cycle Types Selectable With the HCNTL and HR/W Signals Table 4. Access Types Selectable by the HCNTL Signals3.4 HCNTL10 and HR/W Indicating the Cycle Type 3.6 HAS Forcing the HPI to Latch Control Information Early HPI Operation Figure 7. 16-Bit Multiplexed Mode Host Read Cycle Using HASHost Port Interface HPI HPI Operation Figure 8. 16-Bit Multiplexed Mode Host Write Cycle Using HASHost Port Interface HPI 3.7 Performing a Multiplexed Access Without HAS Figure 9. 16-Bit Multiplexed Mode Host Read Cycle With HAS Tied HighHPI Operation Host Port Interface HPI3.8 Single-Halfword HPIC Cycle in the 16-Bit Multiplexed Mode 3.9 Hardware Handshaking Using the HPI-Ready HRDY SignalCase 1 HPIA Write Cycle Followed by Nonautoincrement HPID Read Cycle 3.9.1 HRDY Behavior During 16-Bit Multiplexed Read OperationsCase 2 HPIA Write Cycle Followed by Autoincrement HPID Read Cycles Case 1 No Autoincrementing 3.9.2 HRDY Behavior During 16-Bit Multiplexed Write OperationsCase 2 Autoincrementing Selected, FIFO Empty Before Write Case 3 Autoincrementing Selected, FIFO Not Empty Before Write 3.9.3 HRDY Behavior During 32-Bit Multiplexed Read OperationsCase 2 HPIA Write Cycle Followed by Autoincrement HPID Read Cycles Figure 21 shows an HPIA HCNTL10 = 10b write access followed by several autoincrement HPID HCNTL10 = 01b read accesses. Note that HRDY is active for the HPIA access. HRDY is also active for the first HPID read access, but not for subsequent read accessesCase 1 HPIA Write Cycle Followed by Nonautoincrement HPID Read Cycle 3.9.4 HRDY Behavior During 32-Bit Multiplexed Write OperationsFigure 23 shows an HPIA HCNTL10 = 10b write access followed by an HPID HCNTL10 = 11b write access for 32-bit multiplexed HPI operation Case 1 No AutoincrementingCase 2 Autoincrementing Selected, FIFO Empty Before Write Figure 25 shows an HPIA HCNTL10 = 10b write access when the write FIFO is not empty, followed by several autoincrementing HPID HCNTL10 = 01b write accesses. Note that HRDY is active twice for the HPIA access. This occurs because the FIFO is not empty and the data in the FIFO must first be written to memory. This results in an HRDY assertion immediately after the falling edge of the datastrobe HSTRB. When a write request to memory has been made that will empty the internal FIFO, the HPIA write operation can complete with the rising edge of HSTRB. The second HRDY assertion is for the write to the HPIA register. HRDY is not active for the HPID accessesCase 3 Autoincrementing Selected, FIFO Not Empty Before Write 4 Software Handshaking Using the HPI Ready HRDY Bit 4.1 Polling the HRDY Bit5.1 DSPINT Bit Host-to-CPU Interrupts Figure 26. Host-to-CPU Interrupt State Diagram5 Interrupts Between the Host and the CPU 5.2 HINT Bit CPU-to-Host InterruptsInterrupt active HINT bit=1 HINT signal is low Figure 27. CPU-to-Host Interrupt State DiagramNo interrupt interrupt cleared HINT bit=0 HINT signal is high CPU writes 0 to HINT bit6.1 Read Bursting 6 FIFOs and BurstingFigure 28. FIFOs in the HPI 6.2 Write Bursting 6.4 FIFO Behavior When a Hardware Reset or Software Reset Occurs 6.3 FIFO Flush Conditions7.3 Hardware Reset Considerations 7 Emulation and Reset Considerations7.2 Software Reset Considerations 7.1 Emulation ModesTable 6. Host Port Interface HPI Registers 8 HPI Registers8.1 Introduction HPI RegistersHPI Registers 8.2 Power and Emulation Management Register PWREMUMGMTFigure 29. Power and Emulation Management Register PWREMUMGMT Host Port Interface HPI8.3 Host Port Interface Control Register HPIC Figure 30. Host Access PermissionsFigure 31. CPU Access Permissions Table 8. Host Port Interface Control Register HPIC Field DescriptionsDescription FieldValue For host write cycle8.4 Host Port Interface Address Registers HPIAW and HPIAR LEGEND R = Read only W = Write -n = value after reset31-0 ADDRESS R-0 LEGEND R = Read only -n = value after reset 31-0 ADDRESS R/W-08.5 Data Register HPID Table 10. Data Register HPID Field DescriptionsModified table Appendix A Revision HistoryTable 11. TMS320C6457 HPI Revision History Revision Historyamplifier.ti.com power.ti.comIMPORTANT NOTICE dataconverter.ti.com