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3.9.2HRDY Behavior During 16-Bit Multiplexed Write Operations
Figure 15 shows an HPIC (HCNTL[1:0] = 00b) write cycle during
Figure 15. HRDY Behavior During an HPIC Write Cycle in the
HCS |
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HCNTL[1:0] | 00 | 00 |
HR/W |
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HHWIL |
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Internal |
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HSTRB |
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HD[15:0] | 1st halfword | 2nd halfword |
HRDY |
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Figure 16 includes a HPID write cycle without autoincrementing in the
Figure 16. HRDY Behavior During a Data Write Operation in the
(Case 1: No Autoincrementing)
HPIA write
HCS
HPID write
HCNTL[1:0] 10 10 11 11
HR/W
HHWIL
Internal
HSTRB
1st halfword | 2nd halfword | 1st halfword | 2nd halfword | |||||||
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HD[15:0]
HRDY
Figure 17 shows autoincrement HPID write cycles in the
Figure 17. HRDY Behavior During a Data Write Operation in the
(Case 2: Autoincrementing Selected, FIFO Empty Before Write)
HPIA write
HCS
HPID+ writes
HCNTL[1:0] 10 10 01 01 01 HR/W
HHWIL Internal
HSTRB
1st halfword | 2nd halfword | 1st halfword | 2nd halfword | 1st halfword |
HD[15:0]
HRDY
Figure 18 shows a case similar to that of Figure 17. However, in Figure 18, the write FIFO is not empty when the HPIA access is made. HRDY goes high twice for the first halfword access of the HPIA write cycle. The first HRDY high period is due to the
24 | Host Port Interface (HPI) | SPRUGK7A |
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