Texas Instruments TMS320C6457 manual Appendix a, HDS2 HDS1 HCS, Has

Preface												6
1	Introduction to the HPI											7
	1.1		Summary of the HPI Registers									8
	1.2		Summary of the HPI Signals									9
2	Using the Address Registers											11
	2.1		Single-HPIA Mode									11
	2.2		Dual-HPIA Mode									11
3	HPI Operation											12
	3.1		Host-HPI Signal Connections									12
	3.2		HPI Configuration and Data Flow									14
	3.3					and		Data Strobing and Chip Selection				15
			HDS2,		HDS1,		HCS:
	3.4							Indicating the Cycle Type				16
			HCNTL[1:0] and HR/W:
	3.5		HHWIL: Identifying the First and Second Halfwords in 16-Bit Multiplexed Mode									17
	3.6			Forcing the HPI to Latch Control Information Early								17
			HAS:
	3.7		Performing a Multiplexed Access Without									20
									HAS
	3.8		Single-Halfword HPIC Cycle in the 16-Bit Multiplexed Mode									22
	3.9		Hardware Handshaking Using the HPI-Ready								Signal	22
										(HRDY)
4	Software Handshaking Using the HPI Ready (HRDY) Bit											29
	4.1		Polling the HRDY Bit									29
5	Interrupts Between the Host and the CPU											30
	5.1		DSPINT Bit: Host-to-CPU Interrupts									30
	5.2		HINT Bit: CPU-to-Host Interrupts									30
6	FIFOs and Bursting											32
	6.1		Read Bursting									32
	6.2		Write Bursting									33
	6.3		FIFO Flush Conditions									34
	6.4		FIFO Behavior When a Hardware Reset or Software Reset Occurs									34
7	Emulation and Reset Considerations											35
	7.1		Emulation Modes									35
	7.2		Software Reset Considerations									35
	7.3		Hardware Reset Considerations									35
8	HPI Registers											36
	8.1		Introduction									36
	8.2		Power and Emulation Management Register (PWREMU_MGMT)									37
	8.3		Host Port Interface Control Register (HPIC)									38
	8.4		Host Port Interface Address Registers (HPIAW and HPIAR)									40
	8.5		Data Register (HPID)									41
Appendix A		Revision History										42

SPRUGK7A –March 2009 –Revised July 2010 Table of Contents 3

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