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Texas Instruments TMS320C6457 manual Introduction to the HPI

Models: TMS320C6457

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Introduction to the HPI

Preface																6
1	Introduction to the HPI															7
	1.1		Summary of the HPI Registers													8
	1.2		Summary of the HPI Signals													9
2	Using the Address Registers															11
	2.1		Single-HPIA Mode													11
	2.2		Dual-HPIA Mode													11
3	HPI Operation															12
	3.1		Host-HPI Signal Connections													12
	3.2		HPI Configuration and Data Flow													14
	3.3						and				Data Strobing and Chip Selection					15
	3.3		HDS2,			HDS1,	and	HCS:			Data Strobing and Chip Selection					15
	3.4										Indicating the Cycle Type					16
	3.4		HCNTL[1:0] and HR/W:								Indicating the Cycle Type					16
	3.5		HHWIL: Identifying the First and Second Halfwords in 16-Bit Multiplexed Mode													17
	3.6			Forcing the HPI to Latch Control Information Early												17
	3.6		HAS:	Forcing the HPI to Latch Control Information Early												17
	3.7		Performing a Multiplexed Access Without													20
	3.7		Performing a Multiplexed Access Without									HAS				20
	3.8		Single-Halfword HPIC Cycle in the 16-Bit Multiplexed Mode													22
	3.9		Hardware Handshaking Using the HPI-Ready												Signal	22
	3.9		Hardware Handshaking Using the HPI-Ready											(HRDY)	Signal	22
4	Software Handshaking Using the HPI Ready (HRDY) Bit															29
	4.1		Polling the HRDY Bit													29
5	Interrupts Between the Host and the CPU															30
	5.1		DSPINT Bit: Host-to-CPU Interrupts													30
	5.2		HINT Bit: CPU-to-Host Interrupts													30
6	FIFOs and Bursting															32
	6.1		Read Bursting													32
	6.2		Write Bursting													33
	6.3		FIFO Flush Conditions													34
	6.4		FIFO Behavior When a Hardware Reset or Software Reset Occurs													34
7	Emulation and Reset Considerations															35
	7.1		Emulation Modes													35
	7.2		Software Reset Considerations													35
	7.3		Hardware Reset Considerations													35
8	HPI Registers															36
	8.1		Introduction													36
	8.2		Power and Emulation Management Register (PWREMU_MGMT)													37
	8.3		Host Port Interface Control Register (HPIC)													38
	8.4		Host Port Interface Address Registers (HPIAW and HPIAR)													40
	8.5		Data Register (HPID)													41
Appendix A		Revision History														42

SPRUGK7A –March 2009 –Revised July 2010

Table of Contents

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Copyright © 2009–2010, Texas Instruments Incorporated

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Texas Instruments TMS320C6457 manual Introduction to the HPI

Contents

TMS320C6457 DSP Host Port Interface HPI Users GuideCopyright 2009-2010, Texas Instruments Incorporated SPRUGK7A -March 2009 -Revised JulyIntroduction to the HPI List of Figures List of FiguresList of Tables Notational Conventions Read This FirstPreface About This ManualFigure 1. HPI Position in the Host-DSP System Host Port Interface HPIUsers Guide 1 Introduction to the HPIIntroduction to the HPI 1.1 Summary of the HPI Registers1.2 Summary of the HPI Signals Table 2. HPI SignalsTable 1. Summary of HPI Registers Host Port Interface HPI Table 2. HPI Signalscontinued Introduction to the HPI2 Using the Address Registers 2.1 Single-HPIA Mode2.2 Dual-HPIA Mode 3.1 Host-HPI Signal Connections in the 32-Bit Multiplexed Mode3 HPI Operation in the 16-Bit Multiplexed Mode in the 32-Bit Multiplexed ModeMultiplexed Mode 3.2 HPI Configuration and Data FlowTable 3. Options for Connecting Host and HPI Data Strobe Pins 3.3 HDS2, HDS1, and HCS Data Strobing and Chip SelectionFigure 6. HPI Strobe and Select Logic Table 4. Access Types Selectable by the HCNTL Signals Table 5. Cycle Types Selectable With the HCNTL and HR/W Signals3.4 HCNTL10 and HR/W Indicating the Cycle Type 3.6 HAS Forcing the HPI to Latch Control Information Early Figure 7. 16-Bit Multiplexed Mode Host Read Cycle Using HAS HPI OperationHost Port Interface HPI Figure 8. 16-Bit Multiplexed Mode Host Write Cycle Using HAS HPI OperationHost Port Interface HPI Figure 9. 16-Bit Multiplexed Mode Host Read Cycle With HAS Tied High 3.7 Performing a Multiplexed Access Without HASHost Port Interface HPI HPI Operation3.9 Hardware Handshaking Using the HPI-Ready HRDY Signal 3.8 Single-Halfword HPIC Cycle in the 16-Bit Multiplexed Mode3.9.1 HRDY Behavior During 16-Bit Multiplexed Read Operations Case 1 HPIA Write Cycle Followed by Nonautoincrement HPID Read CycleCase 2 HPIA Write Cycle Followed by Autoincrement HPID Read Cycles 3.9.2 HRDY Behavior During 16-Bit Multiplexed Write Operations Case 1 No AutoincrementingCase 2 Autoincrementing Selected, FIFO Empty Before Write 3.9.3 HRDY Behavior During 32-Bit Multiplexed Read Operations Case 3 Autoincrementing Selected, FIFO Not Empty Before Write3.9.4 HRDY Behavior During 32-Bit Multiplexed Write Operations Figure 21 shows an HPIA HCNTL10 = 10b write access followed by several autoincrement HPID HCNTL10 = 01b read accesses. Note that HRDY is active for the HPIA access. HRDY is also active for the first HPID read access, but not for subsequent read accessesCase 1 HPIA Write Cycle Followed by Nonautoincrement HPID Read Cycle Case 2 HPIA Write Cycle Followed by Autoincrement HPID Read CyclesCase 1 No Autoincrementing Figure 23 shows an HPIA HCNTL10 = 10b write access followed by an HPID HCNTL10 = 11b write access for 32-bit multiplexed HPI operationFigure 25 shows an HPIA HCNTL10 = 10b write access when the write FIFO is not empty, followed by several autoincrementing HPID HCNTL10 = 01b write accesses. Note that HRDY is active twice for the HPIA access. This occurs because the FIFO is not empty and the data in the FIFO must first be written to memory. This results in an HRDY assertion immediately after the falling edge of the datastrobe HSTRB. When a write request to memory has been made that will empty the internal FIFO, the HPIA write operation can complete with the rising edge of HSTRB. The second HRDY assertion is for the write to the HPIA register. HRDY is not active for the HPID accesses Case 2 Autoincrementing Selected, FIFO Empty Before WriteCase 3 Autoincrementing Selected, FIFO Not Empty Before Write 4.1 Polling the HRDY Bit 4 Software Handshaking Using the HPI Ready HRDY Bit5.2 HINT Bit CPU-to-Host Interrupts Figure 26. Host-to-CPU Interrupt State Diagram5 Interrupts Between the Host and the CPU 5.1 DSPINT Bit Host-to-CPU InterruptsCPU writes 0 to HINT bit Figure 27. CPU-to-Host Interrupt State DiagramNo interrupt interrupt cleared HINT bit=0 HINT signal is high Interrupt active HINT bit=1 HINT signal is low6 FIFOs and Bursting 6.1 Read BurstingFigure 28. FIFOs in the HPI 6.2 Write Bursting 6.3 FIFO Flush Conditions 6.4 FIFO Behavior When a Hardware Reset or Software Reset Occurs7.1 Emulation Modes 7 Emulation and Reset Considerations7.2 Software Reset Considerations 7.3 Hardware Reset ConsiderationsHPI Registers 8 HPI Registers8.1 Introduction Table 6. Host Port Interface HPI RegistersHost Port Interface HPI 8.2 Power and Emulation Management Register PWREMUMGMTFigure 29. Power and Emulation Management Register PWREMUMGMT HPI RegistersTable 8. Host Port Interface Control Register HPIC Field Descriptions Figure 30. Host Access PermissionsFigure 31. CPU Access Permissions 8.3 Host Port Interface Control Register HPICFor host write cycle FieldValue Description31-0 ADDRESS R/W-0 LEGEND R = Read only W = Write -n = value after reset31-0 ADDRESS R-0 LEGEND R = Read only -n = value after reset 8.4 Host Port Interface Address Registers HPIAW and HPIARTable 10. Data Register HPID Field Descriptions 8.5 Data Register HPIDRevision History Appendix A Revision HistoryTable 11. TMS320C6457 HPI Revision History Modified tabledataconverter.ti.com power.ti.comIMPORTANT NOTICE amplifier.ti.com