Users Guide | Texas Instruments TMS320C6457 instruction

TMS320C6457 DSP Host Port Interface (HPI)

User's Guide

Literature Number: SPRUGK7A

March 2009 –Revised July 2010

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Texas Instruments TMS320C6457 manual Users Guide

TMS320C6457 specifications

The Texas Instruments TMS320C6457 is a high-performance digital signal processor (DSP) designed for demanding applications in telecommunications, industrial control, and video processing. As part of the TMS320C6000 family, the C6457 combines advanced features with impressive processing capabilities, making it a popular choice among developers looking for efficient and robust solutions.

One of the key features of the TMS320C6457 is its architecture, which is based on the super Harvard architecture. This design separates program and data memory paths, allowing for parallel instruction execution. The C6457 operates at clock speeds of up to 1 GHz, enabling it to deliver peak performance of over 6,000 MIPS (Million Instructions Per Second) and 12,000 MADDs (Multiply-Accumulate operations per second). Such high throughput makes the C6457 suitable for real-time processing applications that require rapid data handling.

The C6457 DSP integrates a rich set of on-chip resources, including up to 1MB of on-chip SRAM, which serves as a fast cache for data and instructions. The device features multiple high-speed interfaces, such as 10/100/1000 Ethernet, Serial RapidIO, and PCI-Express, facilitating seamless connectivity with other devices and systems. Furthermore, the TMS320C6457 supports various communication protocols, allowing it to adapt to a wide range of application scenarios.

In terms of power efficiency, the TMS320C6457 is designed with sophisticated power management features. It includes dynamic voltage and frequency scaling, which adjust power consumption based on workload requirements without compromising performance. This capability is particularly valuable in battery-operated devices or environments where thermal management is critical.

The TMS320C6457 also benefits from extensive software support, including the Texas Instruments DSP/BIOS real-time operating system and Code Composer Studio integrated development environment. Developers can leverage these tools for efficient code development, debugging, and system optimization. Additionally, Texas Instruments provides a range of libraries and algorithms optimized for the C6457, facilitating rapid application development.

Overall, the Texas Instruments TMS320C6457 DSP stands out due to its robust architecture, high processing capabilities, comprehensive connectivity options, and power management features. These attributes make it a versatile solution for a broad spectrum of applications in digital signal processing, where performance and efficiency are paramount. As technology continues to advance, the TMS320C6457 remains a relevant and potent option for developers seeking to push the boundaries of digital signal processing.

Contents

Users Guide SPRUGK7A -March 2009 -Revised July HDS2 HDS1 HCS Appendix aHas List of Figures List of Tables Notational Conventions About This ManualRelated Documentation From Texas Instruments Introduction to the HPI Summary of the HPI Registers HPI Signals Summary of the HPI SignalsSummary of HPI Registers Hstrb HR/WI Hhwili Hasi Single-HPIA Mode Using the Address RegistersDual-HPIA Mode HPI Operation Host-HPI Signal Connections Hhwil HPI Configuration and Data Flow Available Host Data Strobe Pins Options for Connecting Host and HPI Data Strobe PinsHDS2, HDS1, and HCS Data Strobing and Chip Selection Cycle Types Selectable With the Hcntl and HR/W Signals Access Types Selectable by the Hcntl SignalsHCNTL10 and HR/W Indicating the Cycle Type Cycle Type Has Forcing the HPI to Latch Control Information Early Hrdy a Hhwil HCS Has Hrdya Hhwil HCS Has HR/W Hstrb HR/W Performing a Multiplexed Access Without has Bit Multiplexed Mode Host Write Cycle With has Tied High Hardware Handshaking Using the HPI-Ready Hrdy Signal Single-Halfword Hpic Cycle in the 16-Bit Multiplexed Mode Hrdy Hrdy Behavior During 16-Bit Multiplexed Read Operations HR/W Hhwil Hrdy Behavior During 16-Bit Multiplexed Write Operations Hrdy Behavior During 32-Bit Multiplexed Read Operations Hpia Write Hrdy Behavior During 32-Bit Multiplexed Write OperationsHpid Read Hpia Write HPID+ Reads Hpia Write Hpid Write Hpia Write HPID+ Writes Polling the Hrdy Bit Software Handshaking Using the HPI Ready Hrdy Bit Dspint Bit Host-to-CPU Interrupts Interrupts Between the Host and the CPUHint Bit CPU-to-Host Interrupts DSPINT=0 CPU-to-Host Interrupt State Diagram Read Bursting FIFOs and Bursting Write Bursting Fifo Flush Conditions Fifo Behavior When a Hardware Reset or Software Reset Occurs Software Reset Considerations Emulation and Reset ConsiderationsHardware Reset Considerations Emulation Modes Introduction HPI RegistersHost Port Interface HPI Registers Soft Free R/W-0 R/W-0 Power and Emulation Management Register PwremumgmtBit Field Value Description Soft Host Port Interface Control Register Hpic Fetch DualhpiaFor host write cycle HPID/HPIC/HPIAR/HPIAW Address Host Port Interface Address Registers Hpiaw and HpiarBit Field Value Description 31-0 Data Register Hpid Field Descriptions Data Register HpidData HPI data TMS320C6457 HPI Revision History Appendix a Revision HistorySeeAdditions/Modifications/Deletions Rfid Products Applications