Texas Instruments TMS320C6457 manual Introduction to the HPI

User's Guide

SPRUGK7A – March 2009 – Revised July 2010

Host Port Interface (HPI)

This guide describes the host port interface (HPI) on the TMS320C6457 digital signal processors (DSPs). The HPI enables an external host processor (host) to directly access DSP resources (including internal and external memory) using a 16-bit (HPI16) or 32-bit (HPI32) interface.

1Introduction to the HPI

The HPI provides a parallel port interface through which an external host processor (host) can access DSP resources. The HPI enables a host device and CPU to exchange information via internal or external memory. Dedicated address and data registers (HPIA and HPID respectively) within the HPI provide the data path between the external host interface and the processor resources. An HPI control register (HPIC) is available to the host and the CPU for various configuration and interrupt functions.

Figure 1 is a high-level block diagram showing how the HPI connects a host (left side of figure) and the DSP internal resources (right side of figure). The host functions as a master to the HPI. Host activity is asynchronous to the internal clock that drives the HPI. When HPI resources are temporarily busy or unavailable, the HPI informs the host by deasserting the HPI-ready (HRDY) output signal.

Figure 1. HPI Position in the Host-DSP System

Host

Data

Address

ALE

R/W

Chip select

Data strobes

IRQ

Ready

					DSP
		HPI			Internal
	HD[31:0]/HD[15:0]				memory
(if needed)		HPID
	HHWIL	R/W FIFOs
					C64x+
HCNTL0			logic
	Access			Switched	megamodule
		HPIA
HCNTL1			DMA	central
	type
				resource
			HPI		External
					memory
			Increment		I/F
(optional)	HAS
	HR/W	HPIC			Other
	HCS				peripherals
	HDS1, HDS2
	HINT
	HRDY				EDMA3

SPRUGK7A –March 2009 –Revised July 2010 Host Port Interface (HPI) 7

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