Texas Instruments TMS320C6457 manual Interrupts Between the Host and the CPU

Interrupts Between the Host and the CPU www.ti.com

5Interrupts Between the Host and the CPU

The host can interrupt the CPU of the DSP via the DSPINT bit of the HPIC, as described in Section 5.1. The CPU can send an interrupt to the host by using the HINT bit of HPIC, as described in Section 5.2.

5.1DSPINT Bit: Host-to-CPU Interrupts

The DSPINT bit of HPIC allows the host to send an interrupt request to the CPU, as summarized in Figure 26 and detailed following the figure.

Figure 26. Host-to-CPU Interrupt State Diagram

Host writes 0 to DSPINT bit

Host writes 1 to DSPINT bit

(interrupt generated to CPU)(A)

Host writes 0 or 1 to DSPINT bit

No interrupt/
interrupt
cleared	CPU writes 0 or 1
	to DSPINT bit
DSPINT=0
	CPU writes 1
	to DSPINT bit
Interrupt
pending

DSPINT=1

CPU writes 0 to DSPINT bit

AWhen the DSPINT bit transitions from 0 to 1, an interrupt is generated to the CPU. No new interrupt can be generated until the CPU has cleared the bit (DSPINT = 0).

To interrupt the CPU, the host must:

1.Drive both HCNTL1 and HCNTL0 low to request a write to HPIC.

2.Write 1 to the DSPINT bit in HPIC.

When the host sets the DSPINT bit, the HPI generates an interrupt pulse to the CPU that sets the corresponding flag bit in an interrupt flag register of the CPU. If this maskable interrupt is properly enabled in the CPU, the CPU executes the corresponding interrupt service routine (ISR). Before the host can use DSPINT to generate a subsequent interrupt to the CPU, the CPU must acknowledge the current interrupt by writing a 1 to the DSPINT bit. When the CPU writes 1, DSPINT is forced to 0. The host should verify that DSPINT = 0 before generating subsequent interrupts. While DSPINT = 1, host writes to the DSPINT bit do not generate an interrupt pulse.

Writes of 0 have no effect on the DSPINT bit. A hardware reset immediately clears DSPINT and thus clears an active host-to-CPU interrupt.

5.2HINT Bit: CPU-to-Host Interrupts

The HINT bit of HPIC allows the CPU to send an interrupt request to the host, as summarized in Figure 27 and detailed following the figure.

30 Host Port Interface (HPI) SPRUGK7A –March 2009 –Revised July 2010

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