www.ti.comHPI Registers
Table 8. Host Port Interface Control Register (HPIC) Field Descriptions (continued)
Bit | Field | Value | Description | ||
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9 | DUALHPIA |
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| 0 | |||
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| write cycle places the same value in both HPIAR and HPIAW. During autoincrementing, both | ||
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| HPIAR and HPIAW are incremented. A host HPIA read cycle retrieves the value from HPIAR. | ||
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| 1 | |||
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| for write addresses. | ||
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8 | HWOBSTAT |
| HWOB status bit. HWOBSTAT reflects the value of the HWOB bit (see bit 0). | ||
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| 0 | HWOB bit = 0 (first halfword is most significant) | ||
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| 1 | HWOB bit = 1 (first halfword is least significant) | ||
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7 | HPIRST |
| HPI software reset bit (set by CPU). | ||
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| 0 | Host: Reads of HPIRST always return 0. | ||
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| CPU: Once the CPU has written 1 to HPIRST, reads return 0 until the FIFOs are completely reset. | ||
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| Writing 0 before the reset process is complete will not stop the reset from occurring. | ||
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| 1 | CPU: Writing 1 causes the read and write FIFOs and the associated FIFO logic to be reset. As | ||
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| described in Section 7.2, an active host cycle is allowed to complete before the reset process | ||
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| begins. When HPIRST = 1, the | HRDY | pin is deasserted (not ready), thereby holding off all host |
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| accesses. The CPU must set HPIRST = 0 to allow host accesses. | ||
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Reserved | 0 | The host must write 0s to these bits. The CPU cannot modify these bits. | |||
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4 | FETCH |
| Host data fetch command bit (set by host). | ||
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| 0 | CPU/Host: Reads of FETCH always return 0. | ||
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| 1 | Host: Write 1 to tell the HPI DMA logic to | ||
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3 | HRDY |
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| 0 | Host: Internal HRDY is low. The HPI is not ready to complete a host cycle. | ||
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| CPU: Reads of HRDY always return 0. | ||
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| 1 | Host: Internal HRDY is high. The HPI is ready to complete a host cycle. | ||
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| Note: HRDY bit is not the same as the HRDY pin status. Refer to Section 4 for details. | ||
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2 | HINT |
| Host interrupt bit (set by the CPU, cleared by the host). | ||
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| 0 | CPU/Host: Writing 0 has no effect. | ||
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| 1 | CPU: Writing 1 to HINT generates a | ||
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| host or by a hardware reset. | ||
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| Host: Writing 1 to HINT clears HINT to 0, to acknowledge the | ||
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1 | DSPINT |
| DSP interrupt bit (set by the host, cleared by the CPU). | ||
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| 0 | CPU/Host: Writing 0 has no effect. | ||
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| 1 | CPU: Writing 1 to DSPINT clears DSPINT to 0, to acknowledge the | ||
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| Host: Writing 1 to DSPINT generates a | ||
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| by the CPU or by a hardware reset. | ||
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0 | HWOB |
| Halfword order bit (configured by the host). This bit is applicable only in the | ||
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| mode. HWOB must be initialized by the host before the first data or address register access. The | ||
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| status of HWOB is also reflected in HWOBSTAT (see bit 8). | ||
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| For host write cycle: | ||
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| 0 | The first halfword received from the bus is most significant (written to the high half of | ||
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| HPID/HPIC/HPIAR/HPIAW). The second halfword is least significant (written to the low half of | ||
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| HPID/HPIC/HPIAR/HPIAW). | ||
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| 1 | The first halfword received from the bus is least significant (written to the low half of | ||
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| HPID/HPIC/HPIAR/HPIAW). The second halfword is most significant (written to the high half of | ||
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| HPID/HPIC/HPIAR/HPIAW). | ||
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| For host read cycle: | ||
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| 0 | The first halfword transmitted on the bus is most significant (taken from the high half of | ||
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| HPID/HPIC/HPIAR/HPIAW). The second halfword is least significant (taken from the low half of | ||
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| HPID/HPIC/HPIAR/HPIAW). | ||
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| 1 | The first halfword transmitted on the bus is least significant (taken from the low half of | ||
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| HPID/HPIC/HPIAR/HPIAW). The second halfword is most significant (taken from the high half of | ||
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| HPID/HPIC/HPIAR/HPIAW). | ||
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SPRUGK7A | Host Port Interface (HPI) | 39 |
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