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Texas Instruments TMS320C6457 manual HCNTL10 and HR/W Indicating the Cycle Type

Models: TMS320C6457

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3.4HCNTL[1:0] and HR/W: Indicating the Cycle Type

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3.4HCNTL[1:0] and HR/W: Indicating the Cycle Type

The cycle type consists of:

•The access type selected by the host by driving the appropriate levels on the HCNTL[1:0] pins of the HPI. Table 4 describes the four available access types.

•The transfer direction that the host selects with the HR/W pin. The host must drive the HR/W signal high (read) or low (write).

Table 5 summarizes the cycle types. The HPI samples the HCNTL levels either at the falling edge of HAS (if HAS is used) or at the falling edge of the internal strobe signal HSTRB (if HAS is not used or is tied high).

CAUTION

Note that the encoding of HCNTL0 and HCNTL1 for the different types of HPI accesses varies on many TI DSPs; therefore, you should use caution to ensure that the correct encoding of these inputs is used for your device. The encoding of these signals as described in this document applies only to C6457 DSPs.

Table 4. Access Types Selectable by the HCNTL Signals

HCNTL1	HCNTL0	Description
0	0	HPIC access. The host requests to access the HPI control register
		(HPIC).
0	1	HPID access with autoincrementing. The host requests to access the
		HPI data register (HPID) and to have the appropriate HPI address
		register (HPIAR and/or HPIAW) automatically incremented by 1 after
		the access.
1	0	HPIA access. The host requests to access the appropriate HPI
		address register (HPIAR and/or HPIAW).
1	1	HPID access without autoincrementing. The host requests to access
		the HPI data register (HPID) but requests no automatic
		post-increment of the HPI address register.

Table 5. Cycle Types Selectable With the HCNTL and HR/W Signals


HCNTL1	HCNTL0	HR/W		Cycle Type
0	0	0		HPIC write cycle
0	0	1		HPIC read cycle
0	1	0		HPID write cycle with autoincrementing
0	1	1		HPID read cycle with autoincrementing
1	0	0		HPIA write cycle
1	0	1		HPIA read cycle
1	1	0		HPID write cycle without
				autoincrementing
1	1	1		HPID read cycle without
				autoincrementing

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Host Port Interface (HPI)

SPRUGK7A –March 2009 –Revised July 2010

Copyright © 2009–2010, Texas Instruments Incorporated

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Texas Instruments TMS320C6457 HCNTL10 and HR/W Indicating the Cycle Type, Access Types Selectable by the HCNTL Signals

Contents

Users Guide TMS320C6457 DSP Host Port Interface HPISPRUGK7A -March 2009 -Revised July Copyright 2009-2010, Texas Instruments IncorporatedIntroduction to the HPI List of Figures List of FiguresList of Tables Read This First PrefaceAbout This Manual Notational ConventionsHost Port Interface HPI Users Guide1 Introduction to the HPI Figure 1. HPI Position in the Host-DSP System1.1 Summary of the HPI Registers Introduction to the HPITable 2. HPI Signals 1.2 Summary of the HPI SignalsTable 1. Summary of HPI Registers Table 2. HPI Signals continuedIntroduction to the HPI Host Port Interface HPI2.1 Single-HPIA Mode 2 Using the Address Registers2.2 Dual-HPIA Mode in the 32-Bit Multiplexed Mode 3.1 Host-HPI Signal Connections3 HPI Operation in the 32-Bit Multiplexed Mode in the 16-Bit Multiplexed Mode3.2 HPI Configuration and Data Flow Multiplexed Mode3.3 HDS2, HDS1, and HCS Data Strobing and Chip Selection Table 3. Options for Connecting Host and HPI Data Strobe PinsFigure 6. HPI Strobe and Select Logic Table 5. Cycle Types Selectable With the HCNTL and HR/W Signals Table 4. Access Types Selectable by the HCNTL Signals3.4 HCNTL10 and HR/W Indicating the Cycle Type 3.6 HAS Forcing the HPI to Latch Control Information Early HPI Operation Figure 7. 16-Bit Multiplexed Mode Host Read Cycle Using HASHost Port Interface HPI HPI Operation Figure 8. 16-Bit Multiplexed Mode Host Write Cycle Using HASHost Port Interface HPI 3.7 Performing a Multiplexed Access Without HAS Figure 9. 16-Bit Multiplexed Mode Host Read Cycle With HAS Tied HighHPI Operation Host Port Interface HPI3.8 Single-Halfword HPIC Cycle in the 16-Bit Multiplexed Mode 3.9 Hardware Handshaking Using the HPI-Ready HRDY SignalCase 1 HPIA Write Cycle Followed by Nonautoincrement HPID Read Cycle 3.9.1 HRDY Behavior During 16-Bit Multiplexed Read OperationsCase 2 HPIA Write Cycle Followed by Autoincrement HPID Read Cycles Case 1 No Autoincrementing 3.9.2 HRDY Behavior During 16-Bit Multiplexed Write OperationsCase 2 Autoincrementing Selected, FIFO Empty Before Write Case 3 Autoincrementing Selected, FIFO Not Empty Before Write 3.9.3 HRDY Behavior During 32-Bit Multiplexed Read OperationsFigure 21 shows an HPIA HCNTL10 = 10b write access followed by several autoincrement HPID HCNTL10 = 01b read accesses. Note that HRDY is active for the HPIA access. HRDY is also active for the first HPID read access, but not for subsequent read accesses Case 1 HPIA Write Cycle Followed by Nonautoincrement HPID Read CycleCase 2 HPIA Write Cycle Followed by Autoincrement HPID Read Cycles 3.9.4 HRDY Behavior During 32-Bit Multiplexed Write OperationsFigure 23 shows an HPIA HCNTL10 = 10b write access followed by an HPID HCNTL10 = 11b write access for 32-bit multiplexed HPI operation Case 1 No AutoincrementingCase 2 Autoincrementing Selected, FIFO Empty Before Write Figure 25 shows an HPIA HCNTL10 = 10b write access when the write FIFO is not empty, followed by several autoincrementing HPID HCNTL10 = 01b write accesses. Note that HRDY is active twice for the HPIA access. This occurs because the FIFO is not empty and the data in the FIFO must first be written to memory. This results in an HRDY assertion immediately after the falling edge of the datastrobe HSTRB. When a write request to memory has been made that will empty the internal FIFO, the HPIA write operation can complete with the rising edge of HSTRB. The second HRDY assertion is for the write to the HPIA register. HRDY is not active for the HPID accessesCase 3 Autoincrementing Selected, FIFO Not Empty Before Write 4 Software Handshaking Using the HPI Ready HRDY Bit 4.1 Polling the HRDY BitFigure 26. Host-to-CPU Interrupt State Diagram 5 Interrupts Between the Host and the CPU5.1 DSPINT Bit Host-to-CPU Interrupts 5.2 HINT Bit CPU-to-Host InterruptsFigure 27. CPU-to-Host Interrupt State Diagram No interrupt interrupt cleared HINT bit=0 HINT signal is highInterrupt active HINT bit=1 HINT signal is low CPU writes 0 to HINT bit6.1 Read Bursting 6 FIFOs and BurstingFigure 28. FIFOs in the HPI 6.2 Write Bursting 6.4 FIFO Behavior When a Hardware Reset or Software Reset Occurs 6.3 FIFO Flush Conditions7 Emulation and Reset Considerations 7.2 Software Reset Considerations7.3 Hardware Reset Considerations 7.1 Emulation Modes8 HPI Registers 8.1 IntroductionTable 6. Host Port Interface HPI Registers HPI Registers8.2 Power and Emulation Management Register PWREMUMGMT Figure 29. Power and Emulation Management Register PWREMUMGMTHPI Registers Host Port Interface HPIFigure 30. Host Access Permissions Figure 31. CPU Access Permissions8.3 Host Port Interface Control Register HPIC Table 8. Host Port Interface Control Register HPIC Field DescriptionsField ValueDescription For host write cycleLEGEND R = Read only W = Write -n = value after reset 31-0 ADDRESS R-0 LEGEND R = Read only -n = value after reset8.4 Host Port Interface Address Registers HPIAW and HPIAR 31-0 ADDRESS R/W-08.5 Data Register HPID Table 10. Data Register HPID Field DescriptionsAppendix A Revision History Table 11. TMS320C6457 HPI Revision HistoryModified table Revision Historypower.ti.com IMPORTANT NOTICEamplifier.ti.com dataconverter.ti.com