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Texas Instruments TMS320C6457 16-Bit Multiplexed Mode Host Write Cycle Using HAS, HPI Operation

Models: TMS320C6457

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Figure 8. 16-Bit Multiplexed Mode Host Write Cycle Using HAS

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HPI Operation

Figure 8. 16-Bit Multiplexed Mode Host Write Cycle Using HAS

HCS

HAS

HR/W

HCNTL[1:0]

Internal

HSTRB

HD[15:0]

Data 1

Data 2

HRDYA

HHWIL

HPI latches	HPI latches
control information	control information
	HPI latches	HPI latches
	data	data

ADepending on the type of write operation (HPID without autoincrementing, HPIA, HPIC, or HPID with autoincrementing) and the state of the FIFO, transitions on HRDY may or may not occur. For more information, see Section 3.9.

SPRUGK7A –March 2009 –Revised July 2010

Host Port Interface (HPI)

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Texas Instruments TMS320C6457 16-Bit Multiplexed Mode Host Write Cycle Using HAS, HPI Operation, Host Port Interface HPI

Contents

TMS320C6457 DSP Host Port Interface HPI Users GuideCopyright 2009-2010, Texas Instruments Incorporated SPRUGK7A -March 2009 -Revised JulyIntroduction to the HPI List of Figures List of FiguresList of Tables Notational Conventions Read This FirstPreface About This ManualFigure 1. HPI Position in the Host-DSP System Host Port Interface HPIUsers Guide 1 Introduction to the HPIIntroduction to the HPI 1.1 Summary of the HPI RegistersTable 2. HPI Signals 1.2 Summary of the HPI SignalsTable 1. Summary of HPI Registers Host Port Interface HPI Table 2. HPI Signalscontinued Introduction to the HPI2.1 Single-HPIA Mode 2 Using the Address Registers2.2 Dual-HPIA Mode in the 32-Bit Multiplexed Mode 3.1 Host-HPI Signal Connections3 HPI Operation in the 16-Bit Multiplexed Mode in the 32-Bit Multiplexed ModeMultiplexed Mode 3.2 HPI Configuration and Data Flow3.3 HDS2, HDS1, and HCS Data Strobing and Chip Selection Table 3. Options for Connecting Host and HPI Data Strobe PinsFigure 6. HPI Strobe and Select Logic Table 5. Cycle Types Selectable With the HCNTL and HR/W Signals Table 4. Access Types Selectable by the HCNTL Signals3.4 HCNTL10 and HR/W Indicating the Cycle Type 3.6 HAS Forcing the HPI to Latch Control Information Early HPI Operation Figure 7. 16-Bit Multiplexed Mode Host Read Cycle Using HASHost Port Interface HPI HPI Operation Figure 8. 16-Bit Multiplexed Mode Host Write Cycle Using HASHost Port Interface HPI Figure 9. 16-Bit Multiplexed Mode Host Read Cycle With HAS Tied High 3.7 Performing a Multiplexed Access Without HASHost Port Interface HPI HPI Operation3.9 Hardware Handshaking Using the HPI-Ready HRDY Signal 3.8 Single-Halfword HPIC Cycle in the 16-Bit Multiplexed ModeCase 1 HPIA Write Cycle Followed by Nonautoincrement HPID Read Cycle 3.9.1 HRDY Behavior During 16-Bit Multiplexed Read OperationsCase 2 HPIA Write Cycle Followed by Autoincrement HPID Read Cycles Case 1 No Autoincrementing 3.9.2 HRDY Behavior During 16-Bit Multiplexed Write OperationsCase 2 Autoincrementing Selected, FIFO Empty Before Write 3.9.3 HRDY Behavior During 32-Bit Multiplexed Read Operations Case 3 Autoincrementing Selected, FIFO Not Empty Before Write3.9.4 HRDY Behavior During 32-Bit Multiplexed Write Operations Figure 21 shows an HPIA HCNTL10 = 10b write access followed by several autoincrement HPID HCNTL10 = 01b read accesses. Note that HRDY is active for the HPIA access. HRDY is also active for the first HPID read access, but not for subsequent read accessesCase 1 HPIA Write Cycle Followed by Nonautoincrement HPID Read Cycle Case 2 HPIA Write Cycle Followed by Autoincrement HPID Read CyclesCase 1 No Autoincrementing Figure 23 shows an HPIA HCNTL10 = 10b write access followed by an HPID HCNTL10 = 11b write access for 32-bit multiplexed HPI operationCase 2 Autoincrementing Selected, FIFO Empty Before Write Figure 25 shows an HPIA HCNTL10 = 10b write access when the write FIFO is not empty, followed by several autoincrementing HPID HCNTL10 = 01b write accesses. Note that HRDY is active twice for the HPIA access. This occurs because the FIFO is not empty and the data in the FIFO must first be written to memory. This results in an HRDY assertion immediately after the falling edge of the datastrobe HSTRB. When a write request to memory has been made that will empty the internal FIFO, the HPIA write operation can complete with the rising edge of HSTRB. The second HRDY assertion is for the write to the HPIA register. HRDY is not active for the HPID accessesCase 3 Autoincrementing Selected, FIFO Not Empty Before Write 4.1 Polling the HRDY Bit 4 Software Handshaking Using the HPI Ready HRDY Bit5.2 HINT Bit CPU-to-Host Interrupts Figure 26. Host-to-CPU Interrupt State Diagram5 Interrupts Between the Host and the CPU 5.1 DSPINT Bit Host-to-CPU InterruptsCPU writes 0 to HINT bit Figure 27. CPU-to-Host Interrupt State DiagramNo interrupt interrupt cleared HINT bit=0 HINT signal is high Interrupt active HINT bit=1 HINT signal is low6.1 Read Bursting 6 FIFOs and BurstingFigure 28. FIFOs in the HPI 6.2 Write Bursting 6.3 FIFO Flush Conditions 6.4 FIFO Behavior When a Hardware Reset or Software Reset Occurs7.1 Emulation Modes 7 Emulation and Reset Considerations7.2 Software Reset Considerations 7.3 Hardware Reset ConsiderationsHPI Registers 8 HPI Registers8.1 Introduction Table 6. Host Port Interface HPI RegistersHost Port Interface HPI 8.2 Power and Emulation Management Register PWREMUMGMTFigure 29. Power and Emulation Management Register PWREMUMGMT HPI RegistersTable 8. Host Port Interface Control Register HPIC Field Descriptions Figure 30. Host Access PermissionsFigure 31. CPU Access Permissions 8.3 Host Port Interface Control Register HPICFor host write cycle FieldValue Description31-0 ADDRESS R/W-0 LEGEND R = Read only W = Write -n = value after reset31-0 ADDRESS R-0 LEGEND R = Read only -n = value after reset 8.4 Host Port Interface Address Registers HPIAW and HPIARTable 10. Data Register HPID Field Descriptions 8.5 Data Register HPIDRevision History Appendix A Revision HistoryTable 11. TMS320C6457 HPI Revision History Modified tabledataconverter.ti.com power.ti.comIMPORTANT NOTICE amplifier.ti.com