Users Guide
TMS320C6457 DSP Host Port Interface HPI
SPRUGK7A -March 2009 -Revised July
Copyright 2009-2010, Texas Instruments Incorporated
Introduction to the HPI
List of Figures
List of Figures
List of Tables
About This Manual
Read This First
Preface
Notational Conventions
1 Introduction to the HPI
Host Port Interface HPI
Users Guide
Figure 1. HPI Position in the Host-DSP System
1.1 Summary of the HPI Registers
Introduction to the HPI
Table 1. Summary of HPI Registers
1.2 Summary of the HPI Signals
Table 2. HPI Signals
Introduction to the HPI
Table 2. HPI Signals
continued
Host Port Interface HPI
2.2 Dual-HPIA Mode
2 Using the Address Registers
2.1 Single-HPIA Mode
3 HPI Operation
3.1 Host-HPI Signal Connections
in the 32-Bit Multiplexed Mode
in the 32-Bit Multiplexed Mode
in the 16-Bit Multiplexed Mode
3.2 HPI Configuration and Data Flow
Multiplexed Mode
Figure 6. HPI Strobe and Select Logic
Table 3. Options for Connecting Host and HPI Data Strobe Pins
3.3 HDS2, HDS1, and HCS Data Strobing and Chip Selection
3.4 HCNTL10 and HR/W Indicating the Cycle Type
Table 4. Access Types Selectable by the HCNTL Signals
Table 5. Cycle Types Selectable With the HCNTL and HR/W Signals
3.6 HAS Forcing the HPI to Latch Control Information Early
Host Port Interface HPI
Figure 7. 16-Bit Multiplexed Mode Host Read Cycle Using HAS
HPI Operation
Host Port Interface HPI
Figure 8. 16-Bit Multiplexed Mode Host Write Cycle Using HAS
HPI Operation
3.7 Performing a Multiplexed Access Without HAS
Figure 9. 16-Bit Multiplexed Mode Host Read Cycle With HAS Tied High
HPI Operation
Host Port Interface HPI
3.8 Single-Halfword HPIC Cycle in the 16-Bit Multiplexed Mode
3.9 Hardware Handshaking Using the HPI-Ready HRDY Signal
Case 2 HPIA Write Cycle Followed by Autoincrement HPID Read Cycles
3.9.1 HRDY Behavior During 16-Bit Multiplexed Read Operations
Case 1 HPIA Write Cycle Followed by Nonautoincrement HPID Read Cycle
Case 2 Autoincrementing Selected, FIFO Empty Before Write
3.9.2 HRDY Behavior During 16-Bit Multiplexed Write Operations
Case 1 No Autoincrementing
Case 3 Autoincrementing Selected, FIFO Not Empty Before Write
3.9.3 HRDY Behavior During 32-Bit Multiplexed Read Operations
Case 2 HPIA Write Cycle Followed by Autoincrement HPID Read Cycles
Figure 21 shows an HPIA HCNTL10 = 10b write access followed by several autoincrement HPID HCNTL10 = 01b read accesses. Note that HRDY is active for the HPIA access. HRDY is also active for the first HPID read access, but not for subsequent read accesses
Case 1 HPIA Write Cycle Followed by Nonautoincrement HPID Read Cycle
3.9.4 HRDY Behavior During 32-Bit Multiplexed Write Operations
Figure 23 shows an HPIA HCNTL10 = 10b write access followed by an HPID HCNTL10 = 11b write access for 32-bit multiplexed HPI operation
Case 1 No Autoincrementing
Case 3 Autoincrementing Selected, FIFO Not Empty Before Write
Figure 25 shows an HPIA HCNTL10 = 10b write access when the write FIFO is not empty, followed by several autoincrementing HPID HCNTL10 = 01b write accesses. Note that HRDY is active twice for the HPIA access. This occurs because the FIFO is not empty and the data in the FIFO must first be written to memory. This results in an HRDY assertion immediately after the falling edge of the datastrobe HSTRB. When a write request to memory has been made that will empty the internal FIFO, the HPIA write operation can complete with the rising edge of HSTRB. The second HRDY assertion is for the write to the HPIA register. HRDY is not active for the HPID accesses
Case 2 Autoincrementing Selected, FIFO Empty Before Write
4 Software Handshaking Using the HPI Ready HRDY Bit
4.1 Polling the HRDY Bit
5.1 DSPINT Bit Host-to-CPU Interrupts
Figure 26. Host-to-CPU Interrupt State Diagram
5 Interrupts Between the Host and the CPU
5.2 HINT Bit CPU-to-Host Interrupts
Interrupt active HINT bit=1 HINT signal is low
Figure 27. CPU-to-Host Interrupt State Diagram
No interrupt interrupt cleared HINT bit=0 HINT signal is high
CPU writes 0 to HINT bit
Figure 28. FIFOs in the HPI
6 FIFOs and Bursting
6.1 Read Bursting
6.2 Write Bursting
6.4 FIFO Behavior When a Hardware Reset or Software Reset Occurs
6.3 FIFO Flush Conditions
7.3 Hardware Reset Considerations
7 Emulation and Reset Considerations
7.2 Software Reset Considerations
7.1 Emulation Modes
Table 6. Host Port Interface HPI Registers
8 HPI Registers
8.1 Introduction
HPI Registers
HPI Registers
8.2 Power and Emulation Management Register PWREMUMGMT
Figure 29. Power and Emulation Management Register PWREMUMGMT
Host Port Interface HPI
8.3 Host Port Interface Control Register HPIC
Figure 30. Host Access Permissions
Figure 31. CPU Access Permissions
Table 8. Host Port Interface Control Register HPIC Field Descriptions
Description
Field
Value
For host write cycle
8.4 Host Port Interface Address Registers HPIAW and HPIAR
LEGEND R = Read only W = Write -n = value after reset
31-0 ADDRESS R-0 LEGEND R = Read only -n = value after reset
31-0 ADDRESS R/W-0
8.5 Data Register HPID
Table 10. Data Register HPID Field Descriptions
Modified table
Appendix A Revision History
Table 11. TMS320C6457 HPI Revision History
Revision History
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IMPORTANT NOTICE
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![Figure 21 shows an HPIA (HCNTL[1:0] = 10b) write access followed by several autoincrement HPID (HCNTL[1:0] = 01b) read accesses. Note that HRDY is active for the HPIA access. HRDY is also active for the first HPID read access, but not for subsequent read accesses.](/images/new-backgrounds/123146/12314651x1.webp)
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