Texas Instruments TMS320C6457 manual List of Figures

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List of Figures

1	HPI Position in the Host-DSP System														7
2	Example of Host-DSP Signal Connections When Using the													Signal in the 32-Bit Multiplexed Mode	12
												HAS
3	Example of Host-DSP Signal Connections When the									Signal is Tied High in the 32-Bit Multiplexed
									HAS
	Mode														13
4	Example of Host-DSP Signal Connections When Using the													Signal in the 16-Bit Multiplexed Mode	13
												HAS
5	Example of Host-DSP Signal Connections When the									Signal is Tied High in the 16-Bit Multiplexed
									HAS
	Mode														14
6	HPI Strobe and Select Logic														15
7	16-Bit Multiplexed Mode Host Read Cycle Using														18
							HAS
8	16-Bit Multiplexed Mode Host Write Cycle Using														19
						HAS
9	16-Bit Multiplexed Mode Host Read Cycle With							Tied High							20
					HAS
10	16-Bit Multiplexed Mode Host Write Cycle With							Tied High							21
				HAS
11	16-Bit Multiplexed Mode Single-Halfword HPIC Cycle with												Tied High		22
											HAS
12		Behavior During an HPIC or HPIA Read Cycle in the 16-Bit Multiplexed Mode													23
	HRDY
13			Behavior During a Data Read Operation in the 16-Bit Multiplexed Mode (Case 1: HPIA Write
	HRDY
	Cycle Followed by Nonautoincrement HPID Read Cycle)														23
14			Behavior During a Data Read Operation in the 16-Bit Multiplexed Mode (Case 2: HPIA Write
	HRDY
	Cycle Followed by Autoincrement HPID Read Cycles)														23
15			Behavior During an HPIC Write Cycle in the 16-Bit Multiplexed Mode												24
	HRDY
16			Behavior During a Data Write Operation in the 16-Bit Multiplexed Mode (Case 1: No
	HRDY
	Autoincrementing)														24
17			Behavior During a Data Write Operation in the 16-Bit Multiplexed Mode(Case 2: Autoincrementing
	HRDY
	Selected, FIFO Empty Before Write)														24
18			Behavior During a Data Write Operation in the 16-Bit Multiplexed Mode(Case 3: Autoincrementing
	HRDY
	Selected, FIFO Not Empty Before Write)														25
19			Behavior During an HPIC or HPIA Read Cycle in the 32-Bit Multiplexed Mode												25
	HRDY
20			Behavior During a Data Read Operation in the 16-Bit Multiplexed Mode (Case 1: HPIA Write
	HRDY
	Cycle Followed by Nonautoincrement HPID Read Cycle)														26
21			Behavior During a Data Read Operation in the 32-Bit Multiplexed Mode (Case 2: HPIA Write
	HRDY
	Cycle Followed by Autoincrement HPID Read Cycles)														26
22			Behavior During an HPIC Write Cycle in the 32-Bit Multiplexed Mode												27
	HRDY
23			Behavior During a Data Write Operation in the 32-Bit Multiplexed Mode (Case 1: No
	HRDY
	Autoincrementing)														27
24			Behavior During a Data Write Operation in the 32-Bit Multiplexed Mode (Case 2:
	HRDY
	Autoincrementing Selected, FIFO Empty Before Write)														28
25			Behavior During a Data Write Operation in the 32-Bit Multiplexed Mode (Case 3:
	HRDY
	Autoincrementing Selected, FIFO Not Empty Before Write)														28
26	Host-to-CPU Interrupt State Diagram														30
27	CPU-to-Host Interrupt State Diagram														31
28	FIFOs in the HPI														32
29	Power and Emulation Management Register (PWREMU_MGMT)														37
30	Host Access Permissions														38
31	CPU Access Permissions														38
32	Format of an Address Register (HPIAW or HPIAR) - Host Access Permissions														40
33	Format of an Address Register (HPIAW or HPIAR) - CPU Access Permissions														40
34	Data Register (HPID) (Host access permissions, CPU cannot access HPID)														41

4 List of Figures SPRUGK7A –March 2009 –Revised July 2010

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