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Programming the TMS320DM642
9.2.3DM642 Virtual I2C Register Details
Table 10. Decoder 1 Register
Address | 00h |
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Default | 02h |
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Capture
ReservedPositionCapture Size
Enable
Capture Size | Bit 2 | Bit 1 | Bit 0 | |
Unscaled | 0 | 0 | 0 | |
QSIF – 176 × 120 | 0 | 0 | 1 | |
SIF – 352 × 240 (1/4 NTSC) | 0 | 1 | 0 | |
(default) | ||||
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QCIF – 176 × 144 | 0 | 1 | 1 | |
CIF – 352 × 288 (1/4 PAL) | 1 | 0 | 0 | |
QVGA – 320 × 240 | 1 | 0 | 1 | |
VGA – 640 × 480 | 1 | 1 | 0 | |
Reserved | 1 | 1 | 1 | |
Capture Enable | Bit 3 |
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Disable (default) | 0 |
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Enable | 1 |
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Position | Bit 5 | Bit 4 |
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Quadrant 1 (default) | 0 | 0 |
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Quadrant 2 | 0 | 1 |
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Quadrant 3 | 1 | 0 |
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Quadrant 4 | 1 | 1 |
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Quad 1 | Quad 2 |
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Quad 3 | Quad 4 |
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Scaled capture sizes always take priority over unscaled capture sizes.
Decoder priorities are always such that Decoder 1 is the highest priority, Decoder 2 is the second highest, etc.
For example, if Decoders 1 and 4 are scaled to 1/4 size and Decoders 2 and 3 are unscaled, this display results:
Decoder1 Decoder2
Scaled Unscaled
Decoder2 Decoder4
Unscaled Scaled
28 | TVP5154EVM User's Guide | SLEU069A |
