Texas Instruments TVP5154EVM manual Decoder 3 Register, Decoder 4 Register

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Programming the TMS320DM642

Table 12. Decoder 3 Register

Address	01h
Default	22h
7	6	5	4	3	2	1	0
	Reserved		Position	Capture		Capture Size
				Enable

Capture Size	Bit 2	Bit 1	Bit 0
Unscaled	0	0	0
QSIF – 176 × 120	0	0	1
SIF – 352 × 240 (1/4 NTSC)	0	1	0
(default)
QCIF – 176 × 144	0	1	1
CIF – 352 × 288 (1/4 PAL)	1	0	0
QVGA – 320 × 240	1	0	1
VGA – 640 × 480	1	1	0
Reserved	1	1	1
Capture Enable	Bit 3
Disable (default)	0
Enable	1
Position	Bit 5	Bit 4
Quadrant 1	0	0
Quadrant 2	0	1
Quadrant 3 (default)	1	0
Quadrant 4	1	1

Table 13. Decoder 4 Register

Quad 1	Quad 2
Quad 3	Quad 4

Address	01h
Default	32h
7	6	5		4	3	2	1	0
	Reserved		Position		Capture		Capture Size
					Enable
	Capture Size		Bit 2	Bit 1	Bit 0
	Unscaled		0	0	0
	QSIF – 176 × 120		0	0	1
	SIF – 352 × 240 (1/4 NTSC)		0	1	0
	(default)
	QCIF – 176 × 144		0	1	1
	CIF – 352 × 288 (1/4 PAL)		1	0	0
	QVGA – 320 × 240		1	0	1
	VGA – 640 × 480		1	1	0
	Reserved		1	1	1

30	TVP5154EVM User's Guide	SLEU069A –February 2006 –Revised July 2006
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