IBM EM78P259N/260N manual EM78P260NP/M/KM

Page 10

EM78P259N/260N

8-Bit Microprocessor with OTP ROM

5.2 EM78P260NP/M/KM

Symbol

Pin No.

Type

Function

 

 

 

 

 

 

 

 

P70

16

I/O

General purpose input/output pin

Default value after a power-on reset

 

 

 

 

 

 

 

P60~P67

7~14

I/O

General purpose input/output pin

Open-drain

 

 

 

Default value after a power-on reset

 

 

 

General purpose input/output pin

P50~P57

1~4

I/O

Pull-high/pull-down

17~20

Default value after a power-on reset

 

 

 

 

 

Wake up from sleep mode when the status of the pin changes

 

 

 

“-“ : the input pin of Vin- of the comparator

CIN-, CIN+

13, 12

I

“+” : the input pin of Vin+ of the comparator

CO

11

O

Pin CO is the comparator output

 

 

 

Defined by IOC80 <4:3>

 

 

 

 

OSCI

17

I

Crystal type: Crystal input terminal or external clock input pin

RC type: RC oscillator input pin

 

 

 

OSCO

16

I/O

Crystal type: Crystal input terminal or external clock input pin.

RC type: clock output with a duration of one instruction cycle

 

 

 

External clock signal input

 

 

 

If set as /RESET and remains at logic low, the device will be

/RESET

5

I

reset

Voltage on /RESET/Vpp must not exceed Vdd during normal

 

 

 

 

 

 

mode

 

 

 

 

 

 

 

External Timer/Counter input

TCC, TCCA,

4, 8,

I

TCC is defined by CONT <5>

TCCA is defined by IOC80 <1>

TCCB, TCCC

9, 10

 

TCCB is defined by IOC90 <5>

 

 

 

 

 

 

TCCC is defined by IOC90 <1>

ADC0~ADC3

2, 3,

I

Analog to Digital Converter

18, 19

Defined by ADCON (R9) <1:0>

 

 

IR OUT

14

O

IR mode output pin, capable of driving and sinking

current=20mA when the output voltage drops to 0.7Vdd and

 

 

 

rise to0.3Vdd at Vdd=5V.

VREF

4

I

External reference voltage for ADC

Defined by ADCON (R9) <7>

 

 

 

/INT

7

I

External interrupt pin triggered by a falling or rising edge

Defined by CONT <7>

 

 

 

VDD

15

–

Power supply

VSS

6

–

Ground

4 •

Product Specification (V1.2) 05.18.2007

 

(This specification is subject to change without further notice)

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Contents EM78P259N/260N Elan Microelectronics Corporation Contents Analog-To-Digital Converter ADC Reset and Wake-upTCC/WDT and Prescaler 6.111.3 11.111.2 11.4Doc. Version Revision Description DateGeneral Description FeaturesBit Microprocessor with OTP ROM Pin DIP/SOP Block DiagramPin Assignment Pin DIP/SOP/SSOPPin Description Symbol Pin No Type FunctionEM78P259NP/M EM78P260NP/M/KM 1 R0 Indirect Address Register Function DescriptionOperational Registers 2 R1 Time Clock /CounterEM78P259N/260N Bit Microprocessor with OTP ROM Data Memory Configuration ContBit 5 R4 RAM Select RegisterBit 4 T Bits 5~07 R7 Port Bit 7 ~ Bit 4 C3 ~ C0 Calibrator of internal RC mode6 R5 ~ R6 Port 5 ~ Port Bit 7 ~ Bit8 R8 Aisr ADC Input Select Register 9 R9 Adcon ADC Control Register Bit 3 AdpdBit 5 ~ Bit 3 VOF2 ~ VOF0 Offset voltage bits RA Adoc ADC Offset Calibration RegisterRB Addata Converted Value of ADC Bit 2 ~ Bit 0 Unimplemented, read as ‘0’RD ADDATA1L Converted Value of ADC RC ADDATA1H Converted Value of ADCRE Interrupt Status 2 & Wake-up Control Register 16 R10 ~ R3F RF Interrupt Status 2 RegisterAll of these are 8-bit general-purpose registers Accumulator Special Purpose RegistersControl Register Bit 7 & Bit 6 Not used 3 IOC50 ~ IOC70 I/O Port Control Register4 IOC80 Comparator and Tcca Control Register Bit 4 & Bit 3 COS1 & COS0 Comparator/OP Select bitsTccc signal source Bit 6 Tccben Tccb enable bit 0 = disable TccbBit 4 Tccbte Tccb signal edge Bit 0 Tcccte Tccc signal edgeIOCA0 IR and Tccc Scale Control Register Bit 1 LGP Bit 3 IREBit 2 HF Bit 0 IrouteBit PD57 PD56 PD55 PD54 PD53 PD52 PD51 PD50 IOCB0 Pull-down Control RegisterIOCC0 Open-Drain Control Register Bit OD67 OD66 OD65 OD64 OD63 OD62 OD61 OD60IOCE0 WDT Control & Interrupt Mask Registers IOCD0 Pull-high Control RegisterBit PH57 PH56 PH55 PH54 PH53 PH52 PH51 PH50 = Enable Lpwtif interrupt Lpwtif interrupt enable bit= Disable Lpwtif interrupt IOCF0 Interrupt Mask Register12 IOC51 Tcca Counter 13 IOC61 Tccb Counter14 IOC71 TCCBH/MSB Counter 15 IOC81 Tccc CounterIOCA1 High Time Register 16 IOC91 Low Time RegisterIOCB1 High/Low Time Scale Control Register Bit 2 ~ Bit 0 LTS2 ~ LTS0 Low time scale bits IOCC1 TCC Prescaler CounterTCC prescaler counter can be read and written to TCC/WDT and Prescaler I/O Ports MUXI/O Port and I/O Control Register Circuit for P60 /INT I/O Port and I/O Control Register Circuit for Port 50 ~ P57 Usage of Port 5 Input Change Wake-up/Interrupt Function Reset and Wake-upReset and Wake-up Operation Wake-up Wake-up and InterruptEM78P259N/260N Select Segment Signal Sleep Mode Normal Mode Comparator Address Name Reset Type Bit Following summarizes the initialized values for registersName Reset Type Bit HTR7 HTR6 HTR5 HTR4 HTR3 HTR2 HTR1 HTR0 Aisr Controller Reset Block Diagram TcifT and P Status under Status R3 Register InterruptEvent EM78P259N/260N Reti Interrupt Vector Interrupt Status Priority1.1 R8 Aisr ADC Input Select Register Analog-to-Digital Converter ADCADC Control Register AISR/R8, ADCON/R9, ADOC/RA Bit 7 ~ Bit 3 ADE3 Bit 2 ADE2P54/TCC/VREF Pin Priority High Medium Low 1.2 R9 Adcon AD Control RegisterP54 = ADC is operating While the CPU is operatingRA Adoc AD Offset Calibration Register ADC Sampling Time ADC Operation during Sleep ModeADC Data Register ADDATA/RB, ADDATA1H/RC, ADDATA1L/RD AD Conversion TimeProgramming Process Programming Process/ConsiderationsFollow these steps to obtain data from the ADC ADC Control Register Sample Demo Programs Define a General RegisterDefine a Control Register Define Bits in AdconAD power on Infrared Remote Control Application/PWM Waveform Generation OverviewFunction Description FcarrierIRE Irout IR/PWM Related Status/Data Registers Programming the Related RegistersAddress Name Bit EM78P259N/260N Under Tcca Counter IOC51 Timer/CounterUnder Tccb Counter IOC61 Under Tccc Counter IOC81 Comparator Related Tccx Status/Data RegistersExternal Reference Signal Comparator OutputWake-up from Sleep Mode Using a Comparator as an Operation AmplifierComparator Interrupt Oscillator Modes OscillatorOscillator Modes ConditionsOscillator Type Crystal Oscillator/Ceramic Resonators CrystalFrequency C1pF C2pF External RC Oscillator Mode 18 Serial Mode Crystal/Resonator Circuit DiagramCext Rext Average Fosc 5V, 25C Average Fosc 3V, 25C Internal RC Oscillator ModeInternal Drift Rate RC Frequency Temperature 40C ~ +85C 3V~5.5V TotalExternal Power-on Reset Circuit Power-on ConsiderationsProgrammable WDT Time-out Period EM78P259N Residual Voltage ProtectionVdd EM78P260NWord Word1 Bit12 ~ Bit0 Code OptionCode Option Register Word Word Bit Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 BitBit Microprocessor with OTP ROM Bit 3 HLP = Pulses equal to 8/fc s is regarded as signal= Pulses equal to 32/fc s is regarded as signal default Bit 2 ~ 0 PR2 ~ PR0 Protect BitsInstruction Set Bit 1 & Bit 0 RCM1, RCM0 RC mode selection bitsCustomer ID Register Word Instruction Binary Following are the EM78P259N/260N instruction setMnemonic Operation Status Affected Absolute Maximum Ratings Items RatingSymbol Parameter Condition Min Typ Max Unit DC Electrical CharacteristicsTa=25 C, VDD=5.0V±5%, VSS=0V Internal RC Drift Rate Voltage Min Typ MaxAD Converter Characteristics Vdd=2.5V to 5.5V, Vss=0V, Ta=25CDevice Characteristics Comparator OP CharacteristicsVdd = 5.0V, Vss=0V, Ta=25C Symbol Parameter Conditions Min Typ Max Unit AC Electrical CharacteristicTa=25C, VDD=5V±5%, VSS=0V AC Test Input/Output Waveform Timing DiagramsReset Timing CLK=0 TCC Input Timing CLKS=018-Lead Plastic Dual in line Pdip 300 mil Package TypePackage Information Package Type Pin Count Package Size18-Lead Plastic Small Outline SOP 300 mil 838Lead Plastic Shrink Small Outline Ssop 209 mil 650Lead Plastic Dual-in-line Pdip 300 mil Lead Plastic Small Outline SOP 300 mil Address Trap Detect Quality Assurance and ReliabilityTest Category Test Conditions Remarks
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