IBM EM78P259N/260N manual Interrupt, T and P Status under Status R3 Register, Event

Page 47

EM78P259N/260N

8-Bit Microprocessor with OTP ROM

6.5.2 The T and P Status under STATUS (R3) Register

A reset condition is initiated by one of the following events:

1.Power-on reset

2./RESET pin input "low"

3.WDT time-out (if enabled).

The values of RST, T, and P as listed in the table below, are used to check how the processor wakes up.

Reset Type

 

RST

 

T

P

 

 

 

 

Power-on

 

0

 

1

1

/RESET during Operating mode

 

0

 

*P

*P

/RESET wake-up during Sleep mode

 

0

 

1

0

WDT during Operating mode

 

0

 

0

1

WDT wake-up during Sleep mode

 

0

 

0

0

Wake-up on pin change during Sleep mode

 

1

 

1

0

*P: Previous status before reset

The following shows the events that may affect the status of T and P.

Event

RST

 

T

P

 

 

 

 

Power-on

0

 

1

1

WDTC instruction

*P

 

1

1

WDT time-out

0

 

0

*P

SLEP instruction

*P

 

1

0

Wake-up on pin changed during Sleep mode

1

 

1

0

*P: Previous value before reset

6.6 Interrupt

The EM78P259N/260N has six interrupts as listed below:

1.TCC, TCCA, TCCB, TCCC overflow interrupt

2.Port 5 Input Status Change Interrupt

3.External interrupt [(P60, /INT) pin]

4.Analog to Digital conversion completed

5.IR/PWM underflow interrupt

6.When the comparators status changes

Before the Port 5 Input Status Change Interrupt is enabled, reading Port 5 (e.g. "MOV R5,R5") is necessary. Each Port 5 pin will have this feature if its status changes. The Port 5 Input Status Change Interrupt will wake-up the EM78P259N/260N from the sleep mode if it is enabled prior to going into the sleep mode by executing SLEP instruction. When wake-up occurs, the controller will continue to execute program in-line if the global interrupt is disabled. If enabled, the global interrupt will branch out to the interrupt Vector 006H.

Product Specification (V1.2) 05.18.2007

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(This specification is subject to change without further notice)

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Contents EM78P259N/260N Elan Microelectronics Corporation Contents 6.1 Reset and Wake-upTCC/WDT and Prescaler Analog-To-Digital Converter ADC11.4 11.111.2 11.3Date Doc. Version Revision DescriptionBit Microprocessor with OTP ROM FeaturesGeneral Description Pin DIP/SOP/SSOP Block DiagramPin Assignment Pin DIP/SOPEM78P259NP/M Symbol Pin No Type FunctionPin Description EM78P260NP/M/KM 2 R1 Time Clock /Counter Function DescriptionOperational Registers 1 R0 Indirect Address RegisterEM78P259N/260N Cont Bit Microprocessor with OTP ROM Data Memory ConfigurationBits 5~0 5 R4 RAM Select RegisterBit 4 T BitBit 7 ~ Bit Bit 7 ~ Bit 4 C3 ~ C0 Calibrator of internal RC mode6 R5 ~ R6 Port 5 ~ Port 7 R7 Port8 R8 Aisr ADC Input Select Register Bit 3 Adpd 9 R9 Adcon ADC Control RegisterBit 2 ~ Bit 0 Unimplemented, read as ‘0’ RA Adoc ADC Offset Calibration RegisterRB Addata Converted Value of ADC Bit 5 ~ Bit 3 VOF2 ~ VOF0 Offset voltage bitsRE Interrupt Status 2 & Wake-up Control Register RC ADDATA1H Converted Value of ADCRD ADDATA1L Converted Value of ADC All of these are 8-bit general-purpose registers RF Interrupt Status 2 Register16 R10 ~ R3F Control Register Special Purpose RegistersAccumulator Bit 4 & Bit 3 COS1 & COS0 Comparator/OP Select bits 3 IOC50 ~ IOC70 I/O Port Control Register4 IOC80 Comparator and Tcca Control Register Bit 7 & Bit 6 Not usedBit 0 Tcccte Tccc signal edge Bit 6 Tccben Tccb enable bit 0 = disable TccbBit 4 Tccbte Tccb signal edge Tccc signal sourceIOCA0 IR and Tccc Scale Control Register Bit 0 Iroute Bit 3 IREBit 2 HF Bit 1 LGPBit OD67 OD66 OD65 OD64 OD63 OD62 OD61 OD60 IOCB0 Pull-down Control RegisterIOCC0 Open-Drain Control Register Bit PD57 PD56 PD55 PD54 PD53 PD52 PD51 PD50Bit PH57 PH56 PH55 PH54 PH53 PH52 PH51 PH50 IOCD0 Pull-high Control RegisterIOCE0 WDT Control & Interrupt Mask Registers IOCF0 Interrupt Mask Register Lpwtif interrupt enable bit= Disable Lpwtif interrupt = Enable Lpwtif interrupt13 IOC61 Tccb Counter 12 IOC51 Tcca Counter15 IOC81 Tccc Counter 14 IOC71 TCCBH/MSB CounterIOCB1 High/Low Time Scale Control Register 16 IOC91 Low Time RegisterIOCA1 High Time Register TCC prescaler counter can be read and written to IOCC1 TCC Prescaler CounterBit 2 ~ Bit 0 LTS2 ~ LTS0 Low time scale bits TCC/WDT and Prescaler MUX I/O PortsI/O Port and I/O Control Register Circuit for P60 /INT I/O Port and I/O Control Register Circuit for Port 50 ~ P57 Wake-up Wake-up and Interrupt Reset and Wake-upReset and Wake-up Operation Usage of Port 5 Input Change Wake-up/Interrupt FunctionEM78P259N/260N Select Segment Signal Sleep Mode Normal Mode Comparator Following summarizes the initialized values for registers Address Name Reset Type BitName Reset Type Bit HTR7 HTR6 HTR5 HTR4 HTR3 HTR2 HTR1 HTR0 Aisr Tcif Controller Reset Block DiagramEvent InterruptT and P Status under Status R3 Register EM78P259N/260N Interrupt Vector Interrupt Status Priority RetiBit 7 ~ Bit 3 ADE3 Bit 2 ADE2 Analog-to-Digital Converter ADCADC Control Register AISR/R8, ADCON/R9, ADOC/RA 1.1 R8 Aisr ADC Input Select RegisterP54 1.2 R9 Adcon AD Control RegisterP54/TCC/VREF Pin Priority High Medium Low RA Adoc AD Offset Calibration Register While the CPU is operating= ADC is operating AD Conversion Time ADC Operation during Sleep ModeADC Data Register ADDATA/RB, ADDATA1H/RC, ADDATA1L/RD ADC Sampling TimeFollow these steps to obtain data from the ADC Programming Process/ConsiderationsProgramming Process Define Bits in Adcon Sample Demo Programs Define a General RegisterDefine a Control Register ADC Control RegisterAD power on Overview Infrared Remote Control Application/PWM Waveform GenerationFcarrier Function DescriptionIRE Irout Address Name Bit Programming the Related RegistersIR/PWM Related Status/Data Registers EM78P259N/260N Under Tccb Counter IOC61 Timer/CounterUnder Tcca Counter IOC51 Under Tccc Counter IOC81 Related Tccx Status/Data Registers ComparatorComparator Output External Reference SignalComparator Interrupt Using a Comparator as an Operation AmplifierWake-up from Sleep Mode Conditions OscillatorOscillator Modes Oscillator ModesFrequency C1pF C2pF Crystal Oscillator/Ceramic Resonators CrystalOscillator Type 18 Serial Mode Crystal/Resonator Circuit Diagram External RC Oscillator Mode40C ~ +85C 3V~5.5V Total Internal RC Oscillator ModeInternal Drift Rate RC Frequency Temperature Cext Rext Average Fosc 5V, 25C Average Fosc 3V, 25CProgrammable WDT Time-out Period Power-on ConsiderationsExternal Power-on Reset Circuit EM78P260N Residual Voltage ProtectionVdd EM78P259NWord Bit Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit Code OptionCode Option Register Word Word Word1 Bit12 ~ Bit0Bit 2 ~ 0 PR2 ~ PR0 Protect Bits = Pulses equal to 8/fc s is regarded as signal= Pulses equal to 32/fc s is regarded as signal default Bit Microprocessor with OTP ROM Bit 3 HLPCustomer ID Register Word Bit 1 & Bit 0 RCM1, RCM0 RC mode selection bitsInstruction Set Mnemonic Operation Status Affected Following are the EM78P259N/260N instruction setInstruction Binary Items Rating Absolute Maximum RatingsTa=25 C, VDD=5.0V±5%, VSS=0V DC Electrical CharacteristicsSymbol Parameter Condition Min Typ Max Unit Voltage Min Typ Max Internal RC Drift RateVdd=2.5V to 5.5V, Vss=0V, Ta=25C AD Converter CharacteristicsVdd = 5.0V, Vss=0V, Ta=25C Comparator OP CharacteristicsDevice Characteristics Ta=25C, VDD=5V±5%, VSS=0V AC Electrical CharacteristicSymbol Parameter Conditions Min Typ Max Unit TCC Input Timing CLKS=0 Timing DiagramsReset Timing CLK=0 AC Test Input/Output WaveformPackage Type Pin Count Package Size Package TypePackage Information 18-Lead Plastic Dual in line Pdip 300 mil838 18-Lead Plastic Small Outline SOP 300 mil650 Lead Plastic Shrink Small Outline Ssop 209 milLead Plastic Dual-in-line Pdip 300 mil Lead Plastic Small Outline SOP 300 mil Test Category Test Conditions Remarks Quality Assurance and ReliabilityAddress Trap Detect
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