IBM EM78P259N/260N Reset and Wake-up, Usage of Port 5 Input Change Wake-up/Interrupt Function

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EM78P259N/260N

8-Bit Microprocessor with OTP ROM

6.4.1 Usage of Port 5 Input Change Wake-up/Interrupt Function

(1) Wake-up

(2) Wake-up and Interrupt

(a)Before Sleep

1.Disable WDT

2.Read I/O Port 5 (MOV R5,R5)

3.Execute "ENI" or "DISI"

4.Enable wake-up bit (Set RE ICWE =1)

5.Execute "SLEP" instruction

(b)After wake-up

→ Next instruction

(a)Before Sleep

1.Disable WDT

2.Read I/O Port 5 (MOV R5,R5)

3.Execute "ENI" or "DISI"

4.Enable wake-up bit (Set RE ICWE =1)

5.Enable interrupt (Set IOCF0 ICIE =1)

6.Execute "SLEP" instruction

(b)After wake-up

1.IF "ENI" → Interrupt vector (006H)

2.IF "DISI" → Next instruction

(3) Interrupt

(a)Before Port 5 pin change

1.Read I/O Port 5 (MOV R5,R5)

2.Execute "ENI" or "DISI"

3.Enable interrupt (Set IOCF0 ICIE =1)

(b)After Port 5 pin changed (interrupt)

1.IF "ENI" → Interrupt vector (006H)

2.IF "DISI" → Next instruction

6.5Reset and Wake-up

6.5.1 Reset and Wake-up Operation

A reset is initiated by one of the following events:

1.Power-on reset

2./RESET pin input "low"

3.WDT time-out (if enabled).

The device is kept under reset condition for a period of approximately 18ms3 (except in LXT mode) after the reset is detected. When in LXT mode, the reset time is 500ms. Two choices (18ms3 or 4.5ms4) are available for WDT-time out period. Once a reset occurs, the following functions are performed (the initial Address is 000h):

The oscillator continues running, or will be started (if in sleep mode)

The Program Counter (R2) is set to all "0"

3

4

VDD=5V, WDT Time-out period = 16.5ms ± 30%. VDD=3V, WDT Time-out period = 18ms ± 30%.

VDD=5V, WDT Time-out period = 4.2ms ± 30%. VDD=3V, WDT Time-out period = 4.5ms ± 30%.

Product Specification (V1.2) 05.18.2007

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(This specification is subject to change without further notice)

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Contents EM78P259N/260N Elan Microelectronics Corporation Contents TCC/WDT and Prescaler Reset and Wake-upAnalog-To-Digital Converter ADC 6.111.2 11.111.3 11.4Date Doc. Version Revision DescriptionGeneral Description FeaturesBit Microprocessor with OTP ROM Pin Assignment Block DiagramPin DIP/SOP Pin DIP/SOP/SSOPPin Description Symbol Pin No Type FunctionEM78P259NP/M EM78P260NP/M/KM Operational Registers Function Description1 R0 Indirect Address Register 2 R1 Time Clock /CounterEM78P259N/260N Cont Bit Microprocessor with OTP ROM Data Memory ConfigurationBit 4 T 5 R4 RAM Select RegisterBit Bits 5~06 R5 ~ R6 Port 5 ~ Port Bit 7 ~ Bit 4 C3 ~ C0 Calibrator of internal RC mode7 R7 Port Bit 7 ~ Bit8 R8 Aisr ADC Input Select Register Bit 3 Adpd 9 R9 Adcon ADC Control RegisterRB Addata Converted Value of ADC RA Adoc ADC Offset Calibration RegisterBit 5 ~ Bit 3 VOF2 ~ VOF0 Offset voltage bits Bit 2 ~ Bit 0 Unimplemented, read as ‘0’RD ADDATA1L Converted Value of ADC RC ADDATA1H Converted Value of ADCRE Interrupt Status 2 & Wake-up Control Register 16 R10 ~ R3F RF Interrupt Status 2 RegisterAll of these are 8-bit general-purpose registers Accumulator Special Purpose RegistersControl Register 4 IOC80 Comparator and Tcca Control Register 3 IOC50 ~ IOC70 I/O Port Control RegisterBit 7 & Bit 6 Not used Bit 4 & Bit 3 COS1 & COS0 Comparator/OP Select bitsBit 4 Tccbte Tccb signal edge Bit 6 Tccben Tccb enable bit 0 = disable TccbTccc signal source Bit 0 Tcccte Tccc signal edgeIOCA0 IR and Tccc Scale Control Register Bit 2 HF Bit 3 IREBit 1 LGP Bit 0 IrouteIOCC0 Open-Drain Control Register IOCB0 Pull-down Control RegisterBit PD57 PD56 PD55 PD54 PD53 PD52 PD51 PD50 Bit OD67 OD66 OD65 OD64 OD63 OD62 OD61 OD60IOCE0 WDT Control & Interrupt Mask Registers IOCD0 Pull-high Control RegisterBit PH57 PH56 PH55 PH54 PH53 PH52 PH51 PH50 = Disable Lpwtif interrupt Lpwtif interrupt enable bit= Enable Lpwtif interrupt IOCF0 Interrupt Mask Register13 IOC61 Tccb Counter 12 IOC51 Tcca Counter15 IOC81 Tccc Counter 14 IOC71 TCCBH/MSB CounterIOCA1 High Time Register 16 IOC91 Low Time RegisterIOCB1 High/Low Time Scale Control Register Bit 2 ~ Bit 0 LTS2 ~ LTS0 Low time scale bits IOCC1 TCC Prescaler CounterTCC prescaler counter can be read and written to TCC/WDT and Prescaler MUX I/O PortsI/O Port and I/O Control Register Circuit for P60 /INT I/O Port and I/O Control Register Circuit for Port 50 ~ P57 Reset and Wake-up Operation Reset and Wake-upUsage of Port 5 Input Change Wake-up/Interrupt Function Wake-up Wake-up and InterruptEM78P259N/260N Select Segment Signal Sleep Mode Normal Mode Comparator Following summarizes the initialized values for registers Address Name Reset Type BitName Reset Type Bit HTR7 HTR6 HTR5 HTR4 HTR3 HTR2 HTR1 HTR0 Aisr Tcif Controller Reset Block DiagramT and P Status under Status R3 Register InterruptEvent EM78P259N/260N Interrupt Vector Interrupt Status Priority RetiADC Control Register AISR/R8, ADCON/R9, ADOC/RA Analog-to-Digital Converter ADC1.1 R8 Aisr ADC Input Select Register Bit 7 ~ Bit 3 ADE3 Bit 2 ADE2P54/TCC/VREF Pin Priority High Medium Low 1.2 R9 Adcon AD Control RegisterP54 = ADC is operating While the CPU is operatingRA Adoc AD Offset Calibration Register ADC Data Register ADDATA/RB, ADDATA1H/RC, ADDATA1L/RD ADC Operation during Sleep ModeADC Sampling Time AD Conversion TimeProgramming Process Programming Process/ConsiderationsFollow these steps to obtain data from the ADC Define a Control Register Sample Demo Programs Define a General RegisterADC Control Register Define Bits in AdconAD power on Overview Infrared Remote Control Application/PWM Waveform GenerationFcarrier Function DescriptionIRE Irout IR/PWM Related Status/Data Registers Programming the Related RegistersAddress Name Bit EM78P259N/260N Under Tcca Counter IOC51 Timer/CounterUnder Tccb Counter IOC61 Under Tccc Counter IOC81 Related Tccx Status/Data Registers ComparatorComparator Output External Reference SignalWake-up from Sleep Mode Using a Comparator as an Operation AmplifierComparator Interrupt Oscillator Modes OscillatorOscillator Modes ConditionsOscillator Type Crystal Oscillator/Ceramic Resonators CrystalFrequency C1pF C2pF 18 Serial Mode Crystal/Resonator Circuit Diagram External RC Oscillator ModeInternal Drift Rate RC Frequency Temperature Internal RC Oscillator ModeCext Rext Average Fosc 5V, 25C Average Fosc 3V, 25C 40C ~ +85C 3V~5.5V TotalExternal Power-on Reset Circuit Power-on ConsiderationsProgrammable WDT Time-out Period Vdd Residual Voltage ProtectionEM78P259N EM78P260NCode Option Register Word Code OptionWord Word1 Bit12 ~ Bit0 Word Bit Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit= Pulses equal to 32/fc s is regarded as signal default = Pulses equal to 8/fc s is regarded as signalBit Microprocessor with OTP ROM Bit 3 HLP Bit 2 ~ 0 PR2 ~ PR0 Protect BitsInstruction Set Bit 1 & Bit 0 RCM1, RCM0 RC mode selection bitsCustomer ID Register Word Instruction Binary Following are the EM78P259N/260N instruction setMnemonic Operation Status Affected Items Rating Absolute Maximum RatingsSymbol Parameter Condition Min Typ Max Unit DC Electrical CharacteristicsTa=25 C, VDD=5.0V±5%, VSS=0V Voltage Min Typ Max Internal RC Drift RateVdd=2.5V to 5.5V, Vss=0V, Ta=25C AD Converter CharacteristicsDevice Characteristics Comparator OP CharacteristicsVdd = 5.0V, Vss=0V, Ta=25C Symbol Parameter Conditions Min Typ Max Unit AC Electrical CharacteristicTa=25C, VDD=5V±5%, VSS=0V Reset Timing CLK=0 Timing DiagramsAC Test Input/Output Waveform TCC Input Timing CLKS=0Package Information Package Type18-Lead Plastic Dual in line Pdip 300 mil Package Type Pin Count Package Size838 18-Lead Plastic Small Outline SOP 300 mil650 Lead Plastic Shrink Small Outline Ssop 209 milLead Plastic Dual-in-line Pdip 300 mil Lead Plastic Small Outline SOP 300 mil Address Trap Detect Quality Assurance and ReliabilityTest Category Test Conditions Remarks