IBM EM78P259N/260N manual IOCB0 Pull-down Control Register, IOCC0 Open-Drain Control Register

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EM78P259N/260N

8-Bit Microprocessor with OTP ROM

6.2.7 IOCB0 (Pull-down Control Register)

	Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
	Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
	/PD57	/PD56	/PD55	/PD54	/PD53	/PD52	/PD51	/PD50

Note: The IOCB0 register is both readable and writable

Bit 7 (/PD57): Control bit used to enable the pull-down function of the P57 pin (applicable to EM78P260N only)

0= Enable internal pull-down

1= Disable internal pull-down

Bit 6 (/PD56): Control bit used to enable the pull-down function of the P56 pin (applicable to EM78P260N only)

Bit 5 (/PD55): Control bit used to enable the pull-down function of the P55 pin

Bit 4 (/PD54): Control bit used to enable the pull-down function of the P54 pin

Bit 3 (/PD53): Control bit used to enable the pull-down function of the P53 pin

Bit 2 (/PD52): Control bit used to enable the pull-down function of the P52 pin

Bit 1 (/PD51): Control bit used to enable the pull-down function of the P51 pin

Bit 0 (/PD50): Control bit used to enable the pull-down function of the P50 pin.

6.2.8 IOCC0 (Open-Drain Control Register)

	Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
	Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
	/OD67	/OD66	/OD65	/OD64	/OD63	/OD62	/OD61	/OD60

Note: The IOCC0 register is both readable and writable

Bit 7 (/OD67): Control bit used to enable the open-drain output of the P67 pin 0 = Enable open-drain output

1 = Disable open-drain output

Bit 6 (/OD66): Control bit used to enable the open-drain output of the P66 pin

Bit 5 (/OD65): Control bit used to enable the open-drain output of the P65 pin

Bit 4 (/OD64): Control bit used to enable the open-drain output of the P64 pin

Bit 3 (/OD63): Control bit used to enable the open-drain output of the P63 pin

Bit 2 (/OD62): Control bit used to enable the open-drain output of the P62 pin

Bit 1 (/OD61): Control bit used to enable the open-drain output of the P61 pin

Bit 0 (/OD60): Control bit used to enable the open-drain output of the P60 pin

20 •	Product Specification (V1.2) 05.18.2007
	(This specification is subject to change without further notice)

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Contents EM78P259N/260N Elan Microelectronics Corporation Contents Analog-To-Digital Converter ADC Reset and Wake-upTCC/WDT and Prescaler 6.111.3 11.111.2 11.4Doc. Version Revision Description DateBit Microprocessor with OTP ROM FeaturesGeneral Description Pin DIP/SOP Block DiagramPin Assignment Pin DIP/SOP/SSOPEM78P259NP/M Symbol Pin No Type FunctionPin Description EM78P260NP/M/KM 1 R0 Indirect Address Register Function DescriptionOperational Registers 2 R1 Time Clock /CounterEM78P259N/260N Bit Microprocessor with OTP ROM Data Memory Configuration ContBit 5 R4 RAM Select RegisterBit 4 T Bits 5~07 R7 Port Bit 7 ~ Bit 4 C3 ~ C0 Calibrator of internal RC mode6 R5 ~ R6 Port 5 ~ Port Bit 7 ~ Bit8 R8 Aisr ADC Input Select Register 9 R9 Adcon ADC Control Register Bit 3 AdpdBit 5 ~ Bit 3 VOF2 ~ VOF0 Offset voltage bits RA Adoc ADC Offset Calibration RegisterRB Addata Converted Value of ADC Bit 2 ~ Bit 0 Unimplemented, read as ‘0’RE Interrupt Status 2 & Wake-up Control Register RC ADDATA1H Converted Value of ADCRD ADDATA1L Converted Value of ADC All of these are 8-bit general-purpose registers RF Interrupt Status 2 Register16 R10 ~ R3F Control Register Special Purpose RegistersAccumulator Bit 7 & Bit 6 Not used 3 IOC50 ~ IOC70 I/O Port Control Register4 IOC80 Comparator and Tcca Control Register Bit 4 & Bit 3 COS1 & COS0 Comparator/OP Select bitsTccc signal source Bit 6 Tccben Tccb enable bit 0 = disable TccbBit 4 Tccbte Tccb signal edge Bit 0 Tcccte Tccc signal edgeIOCA0 IR and Tccc Scale Control Register Bit 1 LGP Bit 3 IREBit 2 HF Bit 0 IrouteBit PD57 PD56 PD55 PD54 PD53 PD52 PD51 PD50 IOCB0 Pull-down Control RegisterIOCC0 Open-Drain Control Register Bit OD67 OD66 OD65 OD64 OD63 OD62 OD61 OD60Bit PH57 PH56 PH55 PH54 PH53 PH52 PH51 PH50 IOCD0 Pull-high Control RegisterIOCE0 WDT Control & Interrupt Mask Registers = Enable Lpwtif interrupt Lpwtif interrupt enable bit= Disable Lpwtif interrupt IOCF0 Interrupt Mask Register12 IOC51 Tcca Counter 13 IOC61 Tccb Counter14 IOC71 TCCBH/MSB Counter 15 IOC81 Tccc CounterIOCB1 High/Low Time Scale Control Register 16 IOC91 Low Time RegisterIOCA1 High Time Register TCC prescaler counter can be read and written to IOCC1 TCC Prescaler CounterBit 2 ~ Bit 0 LTS2 ~ LTS0 Low time scale bits TCC/WDT and Prescaler I/O Ports MUXI/O Port and I/O Control Register Circuit for P60 /INT I/O Port and I/O Control Register Circuit for Port 50 ~ P57 Usage of Port 5 Input Change Wake-up/Interrupt Function Reset and Wake-upReset and Wake-up Operation Wake-up Wake-up and InterruptEM78P259N/260N Select Segment Signal Sleep Mode Normal Mode Comparator Address Name Reset Type Bit Following summarizes the initialized values for registersName Reset Type Bit HTR7 HTR6 HTR5 HTR4 HTR3 HTR2 HTR1 HTR0 Aisr Controller Reset Block Diagram TcifEvent InterruptT and P Status under Status R3 Register EM78P259N/260N Reti Interrupt Vector Interrupt Status Priority1.1 R8 Aisr ADC Input Select Register Analog-to-Digital Converter ADCADC Control Register AISR/R8, ADCON/R9, ADOC/RA Bit 7 ~ Bit 3 ADE3 Bit 2 ADE2P54 1.2 R9 Adcon AD Control RegisterP54/TCC/VREF Pin Priority High Medium Low RA Adoc AD Offset Calibration Register While the CPU is operating= ADC is operating ADC Sampling Time ADC Operation during Sleep ModeADC Data Register ADDATA/RB, ADDATA1H/RC, ADDATA1L/RD AD Conversion TimeFollow these steps to obtain data from the ADC Programming Process/ConsiderationsProgramming Process ADC Control Register Sample Demo Programs Define a General RegisterDefine a Control Register Define Bits in AdconAD power on Infrared Remote Control Application/PWM Waveform Generation OverviewFunction Description FcarrierIRE Irout Address Name Bit Programming the Related RegistersIR/PWM Related Status/Data Registers EM78P259N/260N Under Tccb Counter IOC61 Timer/CounterUnder Tcca Counter IOC51 Under Tccc Counter IOC81 Comparator Related Tccx Status/Data RegistersExternal Reference Signal Comparator OutputComparator Interrupt Using a Comparator as an Operation AmplifierWake-up from Sleep Mode Oscillator Modes OscillatorOscillator Modes ConditionsFrequency C1pF C2pF Crystal Oscillator/Ceramic Resonators CrystalOscillator Type External RC Oscillator Mode 18 Serial Mode Crystal/Resonator Circuit DiagramCext Rext Average Fosc 5V, 25C Average Fosc 3V, 25C Internal RC Oscillator ModeInternal Drift Rate RC Frequency Temperature 40C ~ +85C 3V~5.5V TotalProgrammable WDT Time-out Period Power-on ConsiderationsExternal Power-on Reset Circuit EM78P259N Residual Voltage ProtectionVdd EM78P260NWord Word1 Bit12 ~ Bit0 Code OptionCode Option Register Word Word Bit Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 BitBit Microprocessor with OTP ROM Bit 3 HLP = Pulses equal to 8/fc s is regarded as signal= Pulses equal to 32/fc s is regarded as signal default Bit 2 ~ 0 PR2 ~ PR0 Protect BitsCustomer ID Register Word Bit 1 & Bit 0 RCM1, RCM0 RC mode selection bitsInstruction Set Mnemonic Operation Status Affected Following are the EM78P259N/260N instruction setInstruction Binary Absolute Maximum Ratings Items RatingTa=25 C, VDD=5.0V±5%, VSS=0V DC Electrical CharacteristicsSymbol Parameter Condition Min Typ Max Unit Internal RC Drift Rate Voltage Min Typ MaxAD Converter Characteristics Vdd=2.5V to 5.5V, Vss=0V, Ta=25CVdd = 5.0V, Vss=0V, Ta=25C Comparator OP CharacteristicsDevice Characteristics Ta=25C, VDD=5V±5%, VSS=0V AC Electrical CharacteristicSymbol Parameter Conditions Min Typ Max Unit AC Test Input/Output Waveform Timing DiagramsReset Timing CLK=0 TCC Input Timing CLKS=018-Lead Plastic Dual in line Pdip 300 mil Package TypePackage Information Package Type Pin Count Package Size18-Lead Plastic Small Outline SOP 300 mil 838Lead Plastic Shrink Small Outline Ssop 209 mil 650Lead Plastic Dual-in-line Pdip 300 mil Lead Plastic Small Outline SOP 300 mil Test Category Test Conditions Remarks Quality Assurance and ReliabilityAddress Trap Detect