IBM EM78P259N/260N manual Programming Process/Considerations

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EM78P259N/260N

8-Bit Microprocessor with OTP ROM

3.ADWE bit of the RE register is set to “1.” Wake-up from ADC conversion (where it remains in operation during sleep mode).

4.Wake-up and executes the next instruction if ADIE bit of IOCE0 is enabled and the “DISI” instruction is executed.

5.Wake-up and enters into Interrupt vector (Address 0x00C) if ADIE bit of IOCE0 is enabled and the “ENI” instruction is executed.

6.Enters into Interrupt vector (Address 0x00C) if ADIE bit of IOCE0 is enabled and the “ENI” instruction is executed.

The results are fed into the ADDATA, ADDATA1H, and ADDATA1L registers when the conversion is completed. If the ADIE is enabled, the device will wake up. Otherwise, the AD conversion will be shut off, no matter what the status of ADPD bit is.

6.7.6 Programming Process/Considerations

6.7.6.1Programming Process

Follow these steps to obtain data from the ADC:

1.Write to the four bits (ADE3:ADE0) on the R8 (AISR) register to define the characteristics of R5 (digital I/O, analog channels, or voltage reference pin)

2.Write to the R9/ADCON register to configure the AD module:

a)Select the ADC input channel (ADIS1:ADIS0)

b)Define the AD conversion clock rate (CKR1:CKR0)

c)Select the VREFS input source of the ADC

d)Set the ADPD bit to 1 to begin sampling

3.Set the ADWE bit, if the wake-up function is employed

4.Set the ADIE bit, if the interrupt function is employed

5.Write “ENI” instruction, if the interrupt function is employed

6.Set the ADRUN bit to 1

7.Write “SLEP” instruction or Polling.

8.Wait for wake-up, ADRUN bit is cleared (“0” value), interrupt flag (ADIF) to be set “1,” or the ADC interrupt to occur.

9.Read the ADDATA or ADDATA1H and ADDATA1L conversion data registers. If the ADC input channel changes at this time, the ADDATA, ADDATA1H, and ADDATA1L values can be cleared to ‘0’.

10.Clear the interrupt flag bit (ADIF)

11.For the next conversion, go to Step 1 or Step 2 as required. At least 2 Tct is required before the next acquisition starts.

48 •	Product Specification (V1.2) 05.18.2007
	(This specification is subject to change without further notice)

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Contents EM78P259N/260N Elan Microelectronics Corporation Contents Analog-To-Digital Converter ADC Reset and Wake-upTCC/WDT and Prescaler 6.111.3 11.111.2 11.4Doc. Version Revision Description DateFeatures General DescriptionBit Microprocessor with OTP ROM Pin DIP/SOP Block DiagramPin Assignment Pin DIP/SOP/SSOPSymbol Pin No Type Function Pin DescriptionEM78P259NP/M EM78P260NP/M/KM 1 R0 Indirect Address Register Function DescriptionOperational Registers 2 R1 Time Clock /CounterEM78P259N/260N Bit Microprocessor with OTP ROM Data Memory Configuration ContBit 5 R4 RAM Select RegisterBit 4 T Bits 5~07 R7 Port Bit 7 ~ Bit 4 C3 ~ C0 Calibrator of internal RC mode6 R5 ~ R6 Port 5 ~ Port Bit 7 ~ Bit8 R8 Aisr ADC Input Select Register 9 R9 Adcon ADC Control Register Bit 3 AdpdBit 5 ~ Bit 3 VOF2 ~ VOF0 Offset voltage bits RA Adoc ADC Offset Calibration RegisterRB Addata Converted Value of ADC Bit 2 ~ Bit 0 Unimplemented, read as ‘0’RC ADDATA1H Converted Value of ADC RD ADDATA1L Converted Value of ADCRE Interrupt Status 2 & Wake-up Control Register RF Interrupt Status 2 Register 16 R10 ~ R3FAll of these are 8-bit general-purpose registers Special Purpose Registers AccumulatorControl Register Bit 7 & Bit 6 Not used 3 IOC50 ~ IOC70 I/O Port Control Register4 IOC80 Comparator and Tcca Control Register Bit 4 & Bit 3 COS1 & COS0 Comparator/OP Select bitsTccc signal source Bit 6 Tccben Tccb enable bit 0 = disable TccbBit 4 Tccbte Tccb signal edge Bit 0 Tcccte Tccc signal edgeIOCA0 IR and Tccc Scale Control Register Bit 1 LGP Bit 3 IREBit 2 HF Bit 0 IrouteBit PD57 PD56 PD55 PD54 PD53 PD52 PD51 PD50 IOCB0 Pull-down Control RegisterIOCC0 Open-Drain Control Register Bit OD67 OD66 OD65 OD64 OD63 OD62 OD61 OD60IOCD0 Pull-high Control Register IOCE0 WDT Control & Interrupt Mask RegistersBit PH57 PH56 PH55 PH54 PH53 PH52 PH51 PH50 = Enable Lpwtif interrupt Lpwtif interrupt enable bit= Disable Lpwtif interrupt IOCF0 Interrupt Mask Register12 IOC51 Tcca Counter 13 IOC61 Tccb Counter14 IOC71 TCCBH/MSB Counter 15 IOC81 Tccc Counter16 IOC91 Low Time Register IOCA1 High Time RegisterIOCB1 High/Low Time Scale Control Register IOCC1 TCC Prescaler Counter Bit 2 ~ Bit 0 LTS2 ~ LTS0 Low time scale bitsTCC prescaler counter can be read and written to TCC/WDT and Prescaler I/O Ports MUXI/O Port and I/O Control Register Circuit for P60 /INT I/O Port and I/O Control Register Circuit for Port 50 ~ P57 Usage of Port 5 Input Change Wake-up/Interrupt Function Reset and Wake-upReset and Wake-up Operation Wake-up Wake-up and InterruptEM78P259N/260N Select Segment Signal Sleep Mode Normal Mode Comparator Address Name Reset Type Bit Following summarizes the initialized values for registersName Reset Type Bit HTR7 HTR6 HTR5 HTR4 HTR3 HTR2 HTR1 HTR0 Aisr Controller Reset Block Diagram TcifInterrupt T and P Status under Status R3 RegisterEvent EM78P259N/260N Reti Interrupt Vector Interrupt Status Priority1.1 R8 Aisr ADC Input Select Register Analog-to-Digital Converter ADCADC Control Register AISR/R8, ADCON/R9, ADOC/RA Bit 7 ~ Bit 3 ADE3 Bit 2 ADE21.2 R9 Adcon AD Control Register P54/TCC/VREF Pin Priority High Medium LowP54 While the CPU is operating = ADC is operatingRA Adoc AD Offset Calibration Register ADC Sampling Time ADC Operation during Sleep ModeADC Data Register ADDATA/RB, ADDATA1H/RC, ADDATA1L/RD AD Conversion TimeProgramming Process/Considerations Programming ProcessFollow these steps to obtain data from the ADC ADC Control Register Sample Demo Programs Define a General RegisterDefine a Control Register Define Bits in AdconAD power on Infrared Remote Control Application/PWM Waveform Generation OverviewFunction Description FcarrierIRE Irout Programming the Related Registers IR/PWM Related Status/Data RegistersAddress Name Bit EM78P259N/260N Timer/Counter Under Tcca Counter IOC51Under Tccb Counter IOC61 Under Tccc Counter IOC81 Comparator Related Tccx Status/Data RegistersExternal Reference Signal Comparator OutputUsing a Comparator as an Operation Amplifier Wake-up from Sleep ModeComparator Interrupt Oscillator Modes OscillatorOscillator Modes ConditionsCrystal Oscillator/Ceramic Resonators Crystal Oscillator TypeFrequency C1pF C2pF External RC Oscillator Mode 18 Serial Mode Crystal/Resonator Circuit DiagramCext Rext Average Fosc 5V, 25C Average Fosc 3V, 25C Internal RC Oscillator ModeInternal Drift Rate RC Frequency Temperature 40C ~ +85C 3V~5.5V TotalPower-on Considerations External Power-on Reset CircuitProgrammable WDT Time-out Period EM78P259N Residual Voltage ProtectionVdd EM78P260NWord Word1 Bit12 ~ Bit0 Code OptionCode Option Register Word Word Bit Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 BitBit Microprocessor with OTP ROM Bit 3 HLP = Pulses equal to 8/fc s is regarded as signal= Pulses equal to 32/fc s is regarded as signal default Bit 2 ~ 0 PR2 ~ PR0 Protect BitsBit 1 & Bit 0 RCM1, RCM0 RC mode selection bits Instruction SetCustomer ID Register Word Following are the EM78P259N/260N instruction set Instruction BinaryMnemonic Operation Status Affected Absolute Maximum Ratings Items RatingDC Electrical Characteristics Symbol Parameter Condition Min Typ Max UnitTa=25 C, VDD=5.0V±5%, VSS=0V Internal RC Drift Rate Voltage Min Typ MaxAD Converter Characteristics Vdd=2.5V to 5.5V, Vss=0V, Ta=25CComparator OP Characteristics Device CharacteristicsVdd = 5.0V, Vss=0V, Ta=25C AC Electrical Characteristic Symbol Parameter Conditions Min Typ Max UnitTa=25C, VDD=5V±5%, VSS=0V AC Test Input/Output Waveform Timing DiagramsReset Timing CLK=0 TCC Input Timing CLKS=018-Lead Plastic Dual in line Pdip 300 mil Package TypePackage Information Package Type Pin Count Package Size18-Lead Plastic Small Outline SOP 300 mil 838Lead Plastic Shrink Small Outline Ssop 209 mil 650Lead Plastic Dual-in-line Pdip 300 mil Lead Plastic Small Outline SOP 300 mil Quality Assurance and Reliability Address Trap DetectTest Category Test Conditions Remarks