IBM EM78P259N/260N manual RC ADDATA1H Converted Value of ADC, RD ADDATA1L Converted Value of ADC

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EM78P259N/260N

8-Bit Microprocessor with OTP ROM

6.1.12 RC (ADDATA1H: Converted Value of ADC)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

“0”

“0”

“0”

“0”

AD11

AD10

AD9

AD8

 

 

 

 

 

 

 

 

When AD conversion is completed, the result is loaded into the ADDATA1H. The ADRUN bit is cleared, and the ADIF (see Section 6.1.14, RE (Interrupt Status 2 & Wake-up Control Register)) is set.

RC is read only

6.1.13 RD (ADDATA1L: Converted Value of ADC)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

 

 

 

 

 

 

 

 

When AD conversion is completed, the result is loaded into the ADDATA1L. The ADRUN bit is cleared, and the ADIF (see Section 6.1.14, RE (Interrupt Status 2 & Wake-up Control Register)) is set.

RD is read only

6.1.14 RE (Interrupt Status 2 & Wake-up Control Register)

Bit 7

 

Bit 6

Bit 5

 

Bit 4

Bit 3

Bit 2

Bit 1

 

Bit 0

 

 

 

–

 

–

ADIF

 

CMPIF

ADWE

CMPWE

ICWE

 

-

 

 

 

 

 

 

 

 

 

Note: RE <5, 4> can be cleared by instruction but cannot be set

 

 

 

 

 

IOCE0 is the interrupt mask register

 

 

 

 

 

 

 

Reading RE will result to "logic AND" of RE and IOCE0

 

 

 

 

Bit 7

& Bit 6:

Not used

 

 

 

 

 

 

Bit 5

(ADIF):

Interrupt flag for analog to digital conversion. Set when AD

 

 

 

 

conversion is completed. Reset by software

 

 

 

0 = no interrupt occurs

1 = with interrupt request

Bit 4 (CMPIF): Comparator interrupt flag. Set when a change occurs in the output of Comparator. Reset by software.

0 = no interrupt occurs

1 = with interrupt request Bit 3 (ADWE): ADC wake-up enable bit 0 = Disable ADC wake-up 1 = Enable ADC wake-up

When AD Conversion enters sleep mode, this bit must be set to “Enable“.

Product Specification (V1.2) 05.18.2007

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(This specification is subject to change without further notice)

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Contents EM78P259N/260N Elan Microelectronics Corporation Contents 6.1 Reset and Wake-upTCC/WDT and Prescaler Analog-To-Digital Converter ADC11.4 11.111.2 11.3Date Doc. Version Revision DescriptionGeneral Description FeaturesBit Microprocessor with OTP ROM Pin DIP/SOP/SSOP Block DiagramPin Assignment Pin DIP/SOPPin Description Symbol Pin No Type FunctionEM78P259NP/M EM78P260NP/M/KM 2 R1 Time Clock /Counter Function DescriptionOperational Registers 1 R0 Indirect Address RegisterEM78P259N/260N Cont Bit Microprocessor with OTP ROM Data Memory ConfigurationBits 5~0 5 R4 RAM Select RegisterBit 4 T BitBit 7 ~ Bit Bit 7 ~ Bit 4 C3 ~ C0 Calibrator of internal RC mode6 R5 ~ R6 Port 5 ~ Port 7 R7 Port8 R8 Aisr ADC Input Select Register Bit 3 Adpd 9 R9 Adcon ADC Control RegisterBit 2 ~ Bit 0 Unimplemented, read as ‘0’ RA Adoc ADC Offset Calibration RegisterRB Addata Converted Value of ADC Bit 5 ~ Bit 3 VOF2 ~ VOF0 Offset voltage bitsRD ADDATA1L Converted Value of ADC RC ADDATA1H Converted Value of ADCRE Interrupt Status 2 & Wake-up Control Register 16 R10 ~ R3F RF Interrupt Status 2 RegisterAll of these are 8-bit general-purpose registers Accumulator Special Purpose RegistersControl Register Bit 4 & Bit 3 COS1 & COS0 Comparator/OP Select bits 3 IOC50 ~ IOC70 I/O Port Control Register4 IOC80 Comparator and Tcca Control Register Bit 7 & Bit 6 Not usedBit 0 Tcccte Tccc signal edge Bit 6 Tccben Tccb enable bit 0 = disable TccbBit 4 Tccbte Tccb signal edge Tccc signal sourceIOCA0 IR and Tccc Scale Control Register Bit 0 Iroute Bit 3 IREBit 2 HF Bit 1 LGPBit OD67 OD66 OD65 OD64 OD63 OD62 OD61 OD60 IOCB0 Pull-down Control RegisterIOCC0 Open-Drain Control Register Bit PD57 PD56 PD55 PD54 PD53 PD52 PD51 PD50IOCE0 WDT Control & Interrupt Mask Registers IOCD0 Pull-high Control RegisterBit PH57 PH56 PH55 PH54 PH53 PH52 PH51 PH50 IOCF0 Interrupt Mask Register Lpwtif interrupt enable bit= Disable Lpwtif interrupt = Enable Lpwtif interrupt13 IOC61 Tccb Counter 12 IOC51 Tcca Counter15 IOC81 Tccc Counter 14 IOC71 TCCBH/MSB CounterIOCA1 High Time Register 16 IOC91 Low Time RegisterIOCB1 High/Low Time Scale Control Register Bit 2 ~ Bit 0 LTS2 ~ LTS0 Low time scale bits IOCC1 TCC Prescaler CounterTCC prescaler counter can be read and written to TCC/WDT and Prescaler MUX I/O PortsI/O Port and I/O Control Register Circuit for P60 /INT I/O Port and I/O Control Register Circuit for Port 50 ~ P57 Wake-up Wake-up and Interrupt Reset and Wake-upReset and Wake-up Operation Usage of Port 5 Input Change Wake-up/Interrupt FunctionEM78P259N/260N Select Segment Signal Sleep Mode Normal Mode Comparator Following summarizes the initialized values for registers Address Name Reset Type BitName Reset Type Bit HTR7 HTR6 HTR5 HTR4 HTR3 HTR2 HTR1 HTR0 Aisr Tcif Controller Reset Block DiagramT and P Status under Status R3 Register InterruptEvent EM78P259N/260N Interrupt Vector Interrupt Status Priority RetiBit 7 ~ Bit 3 ADE3 Bit 2 ADE2 Analog-to-Digital Converter ADCADC Control Register AISR/R8, ADCON/R9, ADOC/RA 1.1 R8 Aisr ADC Input Select RegisterP54/TCC/VREF Pin Priority High Medium Low 1.2 R9 Adcon AD Control RegisterP54 = ADC is operating While the CPU is operatingRA Adoc AD Offset Calibration Register AD Conversion Time ADC Operation during Sleep ModeADC Data Register ADDATA/RB, ADDATA1H/RC, ADDATA1L/RD ADC Sampling TimeProgramming Process Programming Process/ConsiderationsFollow these steps to obtain data from the ADC Define Bits in Adcon Sample Demo Programs Define a General RegisterDefine a Control Register ADC Control RegisterAD power on Overview Infrared Remote Control Application/PWM Waveform GenerationFcarrier Function DescriptionIRE Irout IR/PWM Related Status/Data Registers Programming the Related RegistersAddress Name Bit EM78P259N/260N Under Tcca Counter IOC51 Timer/CounterUnder Tccb Counter IOC61 Under Tccc Counter IOC81 Related Tccx Status/Data Registers ComparatorComparator Output External Reference SignalWake-up from Sleep Mode Using a Comparator as an Operation AmplifierComparator Interrupt Conditions OscillatorOscillator Modes Oscillator ModesOscillator Type Crystal Oscillator/Ceramic Resonators CrystalFrequency C1pF C2pF 18 Serial Mode Crystal/Resonator Circuit Diagram External RC Oscillator Mode40C ~ +85C 3V~5.5V Total Internal RC Oscillator ModeInternal Drift Rate RC Frequency Temperature Cext Rext Average Fosc 5V, 25C Average Fosc 3V, 25CExternal Power-on Reset Circuit Power-on ConsiderationsProgrammable WDT Time-out Period EM78P260N Residual Voltage ProtectionVdd EM78P259NWord Bit Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit Code OptionCode Option Register Word Word Word1 Bit12 ~ Bit0Bit 2 ~ 0 PR2 ~ PR0 Protect Bits = Pulses equal to 8/fc s is regarded as signal= Pulses equal to 32/fc s is regarded as signal default Bit Microprocessor with OTP ROM Bit 3 HLPInstruction Set Bit 1 & Bit 0 RCM1, RCM0 RC mode selection bitsCustomer ID Register Word Instruction Binary Following are the EM78P259N/260N instruction setMnemonic Operation Status Affected Items Rating Absolute Maximum RatingsSymbol Parameter Condition Min Typ Max Unit DC Electrical CharacteristicsTa=25 C, VDD=5.0V±5%, VSS=0V Voltage Min Typ Max Internal RC Drift RateVdd=2.5V to 5.5V, Vss=0V, Ta=25C AD Converter CharacteristicsDevice Characteristics Comparator OP CharacteristicsVdd = 5.0V, Vss=0V, Ta=25C Symbol Parameter Conditions Min Typ Max Unit AC Electrical CharacteristicTa=25C, VDD=5V±5%, VSS=0V TCC Input Timing CLKS=0 Timing DiagramsReset Timing CLK=0 AC Test Input/Output WaveformPackage Type Pin Count Package Size Package TypePackage Information 18-Lead Plastic Dual in line Pdip 300 mil838 18-Lead Plastic Small Outline SOP 300 mil650 Lead Plastic Shrink Small Outline Ssop 209 milLead Plastic Dual-in-line Pdip 300 mil Lead Plastic Small Outline SOP 300 mil Address Trap Detect Quality Assurance and ReliabilityTest Category Test Conditions Remarks
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